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Journal Articles
- 2019
[j17]Simon R. Girard, Vincent Legault, Guy Bois
, Jean-François Boland:
Avionics Graphics Hardware Performance Prediction with Machine Learning. Sci. Program. 2019: 9195845:1-9195845:15 (2019)- 2016
- [j16]Shervin Vakili, J. M. Pierre Langlois, Guy Bois:
Accuracy-aware processor customisation for fixed-point arithmetic. IET Comput. Digit. Tech. 10(1): 1-11 (2016) - 2013
- [j15]Shervin Vakili, J. M. Pierre Langlois, Guy Bois:
Customised soft processor design: a compromise between architecture description languages and parameterisable processors. IET Comput. Digit. Tech. 7(3) (2013) - [j14]Sébastien Le Beux, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin:
Reduction methods for adapting optical network on chip topologies to 3D architectures. Microprocess. Microsystems 37(1): 87-98 (2013) - [j13]Shervin Vakili, J. M. Pierre Langlois, Guy Bois:
Enhanced Precision Analysis for Accuracy-Aware Bit-Width Optimization Using Affine Arithmetic. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(12): 1853-1865 (2013) - 2010
- [j12]Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin:
Multi-Optical Network-on-Chip for Large Scale MPSoC. IEEE Embed. Syst. Lett. 2(3): 77-80 (2010) - [j11]Sébastien Le Beux, Guy Bois, Gabriela Nicolescu, Youcef Bouchebaba, Michel Langevin, Pierre G. Paulin:
Combining mapping and partitioning exploration for NoC-based embedded systems. J. Syst. Archit. 56(7): 223-232 (2010) - 2009
- [j10]Mohamed H. Zaki, William Denman, Sofiène Tahar, Guy Bois:
Integrating Abstraction Techniques for Formal Verification of Analog Designs. J. Aerosp. Comput. Inf. Commun. 6(5): 373-392 (2009) - [j9]Patrick Mahoney, Yvon Savaria, Guy Bois, Patrice Plante:
Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories. Trans. High Perform. Embed. Archit. Compil. 2: 307-325 (2009) - [j8]Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois:
High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse. J. Signal Process. Syst. 56(2-3): 155-165 (2009) - 2008
- [j7]Mohamed H. Zaki, Sofiène Tahar, Guy Bois:
Formal verification of analog and mixed signal designs: A survey. Microelectron. J. 39(12): 1395-1404 (2008) - 2006
- [j6]Jérôme Chevalier, Maxime de Nanclas, Luc Filion, Olivier Benny, Mathieu Rondonneau, Guy Bois, El Mostapha Aboulhamid:
A SystemC Refinement Methodology for Embedded Software. IEEE Des. Test Comput. 23(2): 148-158 (2006) - 1999
- [j5]Mohamed Nekili, Yvon Savaria, Guy Bois:
Spatial characterization of process variations via MOS transistor time constants in VLSI and WSI. IEEE J. Solid State Circuits 34(1): 80-84 (1999) - [j4]B. Bosi, Guy Bois, Yvon Savaria:
Reconfigurable pipelined 2-D convolvers for fast digital signal processing. IEEE Trans. Very Large Scale Integr. Syst. 7(3): 299-308 (1999) - 1997
- [j3]Mohamed Nekili, Guy Bois, Yvon Savaria:
Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations. IEEE Trans. Very Large Scale Integr. Syst. 5(2): 161-174 (1997) - 1996
- [j2]Guy Bois, Eduard Cerny:
Efficient generation of diagonal constraints for 2-D mask compaction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(9): 1119-1126 (1996) - 1988
- [j1]Eduard Cerny, El Mostapha Aboulhamid, Guy Bois, Jocelyn Cloutier:
Built-in self-test of a CMOS ALU. IEEE Des. Test 5(4): 38-48 (1988)
Conference and Workshop Papers
- 2024
- [c47]Fabien Portas, Guy Bois, Yvon Savaria:
CoChrono: A Unified Hardware/Software Performance Analysis Tool for SoC-FPGA Codesign. NewCAS 2024: 328-332 - [c46]Julien Posso, Guy Bois, Yvon Savaria:
Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoC. NewCAS 2024: 358-362 - 2022
- [c45]Julien Posso, Guy Bois, Yvon Savaria:
Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation. ISCAS 2022: 794-798 - 2016
- [c44]Alexsandre B. Lacroix, J. M. Pierre Langlois, François-Raymond Boyer, Antoine Gosselin, Guy Bois:
Node configuration for the Aho-Corasick algorithm in Intrusion Detection Systems. ANCS 2016: 121-122 - [c43]Fellipe Montero, Guy Bois, Eric Jenn, Kevin Duplantier:
Architectural exploration and implementation of an image processing chain with SpaceStudio™. FPL 2016: 1 - 2015
- [c42]Shervin Vakili, J. M. Pierre Langlois, Guy Bois:
Designing customized microprocessors for fixed-point computation. AHS 2015: 1 - [c41]Pascal Nsame, Guy Bois, Yvon Savaria:
Analysis and characterization of data energy tradeoffs: For VLSI architectural agility in C-RAN platforms. ISCAS 2015: 1466-1469 - 2014
- [c40]Pascal Nsame, Guy Bois, Yvon Savaria:
A data-driven energy efficient and flexible compute fabric architecture: For adaptive computing applied to ULSI of FFT. ICECS 2014: 750-753 - [c39]Pascal Nsame, Guy Bois, Yvon Savaria:
Adaptive real-time DSP acceleration for SoC applications. MWSCAS 2014: 298-301 - [c38]Pascal Nsame, Guy Bois, Yvon Savaria:
Design and Test of Adaptive Computing Fabrics for Scalable and High-Efficiency Cognitive SoC Applications. NATW 2014: 48-51 - 2013
- [c37]Shervin Vakili, J. M. Pierre Langlois, Guy Bois:
Finite-precision error modeling using affine arithmetic. ICASSP 2013: 2591-2595 - 2011
- [c36]Sébastien Le Beux, Jelena Trajkovic, Ian O'Connor, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin:
Optical Ring Network-on-Chip (ORNoC): Architecture and design methodology. DATE 2011: 788-793 - [c35]Shervin Vakili, Diana Carolina Gil, J. M. Pierre Langlois, Yvon Savaria, Guy Bois:
Customized embedded processor design for global photographic tone mapping. ICECS 2011: 382-385 - [c34]Tennessee Carmel-Veilleux, Jean-François Boland, Guy Bois:
A novel low-overhead flexible instrumentation framework for virtual platforms. International Symposium on Rapid System Prototyping 2011: 92-98 - 2010
- [c33]Michel Rogers-Vallée, Marc-André Cantin, Laurent Moss, Guy Bois:
IP characterization methodology for fast and accurate power consumption estimation at transactional level model. ICCD 2010: 534-541 - [c32]Sébastien Le Beux, Gabriela Nicolescu, Guy Bois, Pierre G. Paulin:
A system-level exploration flow for optica network on chip (ONoC) in 3D MPSoC. ISCAS 2010: 3613-3616 - 2009
- [c31]Sébastien Le Beux, Gabriela Nicolescu, Guy Bois, Youcef Bouchebaba, Michel Langevin, Pierre G. Paulin:
Optimizing Configuration and Application Mapping for MPSoC Architectures. AHS 2009: 474-481 - 2008
- [c30]Sebastien Fontaine, Luc Filion, Guy Bois:
Exploring ISS Abstractions for Embedded Software Design. DSD 2008: 651-655 - [c29]Sebastien Fontaine, Sylvain Goyette, J. M. Pierre Langlois, Guy Bois:
Acceleration of a 3D target tracking algorithm using an application specific instruction set processor. ICCD 2008: 255-259 - [c28]Laurent Moss, Marc-André Cantin, Guy Bois, El Mostapha Aboulhamid:
Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology. IEEE International Workshop on Rapid System Prototyping 2008: 75-81 - 2007
- [c27]Laurent Moss, Maxime de Nanclas, Luc Filion, Sebastien Fontaine, Guy Bois, El Mostapha Aboulhamid:
Seamless hardware/software performance co-monitoring in a codesign simulation environment with RTOS support. DATE 2007: 876-881 - [c26]Mohamed H. Zaki, Ghiath Al Sammane, Sofiène Tahar, Guy Bois:
Combining Symbolic Simulation and Interval Arithmetic for the Verification of AMS Designs. FMCAD 2007: 207-215 - [c25]Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois:
A Methodology to Evaluate the Energy Efficiency of Application Specific Processors. ICECS 2007: 983-986 - [c24]Karim Hadjiat, Francis St-Pierre, Guy Bois, Yvon Savaria, Michel Langevin, Pierre G. Paulin:
An FPGA Implementation of a Scalable Network-on-Chip Based on the Token Ring Concept. ICECS 2007: 995-998 - [c23]Alena Tsikhanovich, El Mostapha Aboulhamid, Guy Bois:
Communication Structure Refinement using Temporal Constraints Analysis. ICECS 2007: 1284-1287 - [c22]Mohamed H. Zaki, Sofiène Tahar, Guy Bois:
Qualitative Abstraction based Verification for Analog Circuits. ISoLA 2007: 147-158 - 2006
- [c21]Alena Tsikhanovich, Frédéric Rousseau, El Mostapha Aboulhamid, Guy Bois:
Transaction Level Modeling in Hardware/Software System Design using .Net Framework. CCECE 2006: 140-143 - [c20]Mohamed H. Zaki, Sofiène Tahar, Guy Bois:
A practical approach for monitoring analog circuits. ACM Great Lakes Symposium on VLSI 2006: 330-335 - [c19]Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois:
Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor. SiPS 2006: 130-135 - [c18]Simon Provost, Bruno Lavigueur, Guy Bois, Gabriela Nicolescu:
Integration of Configurable Processors in a Multiprocessor Platform. SoCC 2006: 221-224 - 2005
- [c17]Alena Tsikhanovich, El Mostapha Aboulhamid, Guy Bois:
A Methodology for Hw/Sw Specification and Simulation at Multiple Levels of Abstraction. IWSOC 2005: 24-29 - [c16]Jean-Francois Thibeault, Mortimer Hubin, François Deslauriers, Patrick Samson, Guy Bois:
A Reprogrammable SoC Design for a Real-Time Control Application. MSE 2005: 73-74 - 2004
- [c15]D. Quinn, Bruno Lavigueur, Guy Bois, El Mostapha Aboulhamid:
A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors. DATE 2004: 364-371 - [c14]James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois:
.NET Framework - A Solution for the Next Generation Tools for System-Level Modeling and Simulation. DATE 2004: 732-733 - [c13]Luc Charest, El Mostapha Aboulhamid, Guy Bois:
Using Design Patterns for Type Unification and Introspection in SystemC. IWSOC 2004: 45-50 - [c12]S. Regimbal, Yvon Savaria, Guy Bois:
Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models. IWSOC 2004: 87-92 - [c11]James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois:
ESys.Net: a new solution for embedded systems modeling and simulation. LCTES 2004: 107-114 - 2003
- [c10]Marc Bertola, Guy Bois:
A methodology for the design of AHB bus master wrappers. DSD 2003: 90-97 - [c9]Jérôme Chevalier, Mathieu Rondonneau, Olivier Benny, Guy Bois, El Mostapha Aboulhamid, François R. Boyer:
SPACE: A Hardware/Software SystemC Modeling Platform Including an RTOS. FDL 2003: 704-716 - [c8]S. Regimbal, Jean-Francois Lemire, Yvon Savaria, Guy Bois, El Mostapha Aboulhamid, A. Baron:
Automating Functional Coverage Analysis Based on an Executable Specification. IWSOC 2003: 228-234 - [c7]Marc Bertola, Guy Bois:
Teaching Bus Architectures with a Basic, Hands-On SOC Platform. MSE 2003: 68- - 2001
- [c6]Luc Charest, Michel Reid, El Mostapha Aboulhamid, Guy Bois:
A methodology for interfacing open source systemC with a third party software. DATE 2001: 16 - [c5]Mohamed Nekili, Yvon Savaria, Guy Bois:
Minimizing process-induced skew using delay tuning. ISCAS (4) 2001: 426-429 - 1999
- [c4]B. Le Chapelain, A. Mechain, Yvon Savaria, Guy Bois:
Development of a high performance TSPC library for implementation of large digital building blocks. ISCAS (1) 1999: 443-446 - 1998
- [c3]Manoucher Shaditalab, Guy Bois, Mohamad Sawan:
Self Sorting Radix_2 FFT on FPGA using Parallel Pipelined Distributed Arithmetic Blocks. FCCM 1998: 337-338 - [c2]Mohamed Nekili, Yvon Savaria, Guy Bois:
Design of Clock Distribution Networks in Presence of Process Variations. Great Lakes Symposium on VLSI 1998: 95-102 - 1994
- [c1]Mohamed Nekili, Yvon Savaria, Guy Bois:
A Fast Low-Power Driver for Long Interconnections in VLSI Systems. ISCAS 1994: 343-346
Parts in Books or Collections
- 2003
- [p1]Luc Charest, El Mostapha Aboulhamid, Guy Bois:
Applying Multi-Paradigm and Design Pattern Approaches to Hardware/Software Design and Reuse. Patterns and Skeletons for Parallel and Distributed Computing 2003: 297-325
Informal and Other Publications
- 2024
- [i2]Julien Posso, Guy Bois, Yvon Savaria:
Real-Time Spacecraft Pose Estimation Using Mixed-Precision Quantized Neural Network on COTS Reconfigurable MPSoC. CoRR abs/2407.06170 (2024) - 2022
- [i1]Julien Posso, Guy Bois, Yvon Savaria:
Mobile-URSONet: an Embeddable Neural Network for Onboard Spacecraft Pose Estimation. CoRR abs/2205.02065 (2022)
Coauthor Index
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