default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSantosh Kumar Vishvakarma
Person information
Refine list
refinements active!
zoomed in on ?? of ?? records
view refined list in
export refined list as
showing all ?? records
2020 – today
- 2024
[j42]Neha Ashar, Gopal Raut
, Vasundhara Trivedi, Santosh Kumar Vishvakarma, Akash Kumar:
QuantMAC: Enhancing Hardware Performance in DNNs With Quantize Enabled Multiply-Accumulate Unit. IEEE Access 12: 43600-43614 (2024)- [j41]Narendra Singh Dhakad, Eshika Chittora, Gopal Raut, Vishal Sharma, Santosh Kumar Vishvakarma:
In-Memory Computing with 6T SRAM for Multi-operator Logic Design. Circuits Syst. Signal Process. 43(1): 646-660 (2024) - [j40]Sudheer Vishwakarma, Gopal Raut, Sonu Jaiswal, Santosh Kumar Vishvakarma, Dhruva Ghai:
A Precision-Aware Neuron Engine for DNN Accelerators. SN Comput. Sci. 5(5): 494 (2024) - [i4]Narendra Singh Dhakad, Santosh Kumar Vishvakarma:
Configurable Multi-Port Memory Architecture for High-Speed Data Communication. CoRR abs/2407.20628 (2024) - [i3]Narendra Singh Dhakad, Yuvnish Malhotra, Santosh Kumar Vishvakarma, Kaushik Roy:
SHA-CNN: Scalable Hierarchical Aware Convolutional Neural Network for Edge AI. CoRR abs/2407.21370 (2024) - [i2]Omkar Kokane, Prabhat Sati, Mukul Lokhande, Santosh Kumar Vishvakarma:
HOAA: Hybrid Overestimating Approximate Adder for Enhanced Performance Processing Engine. CoRR abs/2408.00806 (2024) - [i1]Sonu Kumar, Komal Gupta, Gopal Raut, Mukul Lokhande, Santosh Kumar Vishvakarma:
HYDRA: Hybrid Data Multiplexing and Run-time Layer Configurable DNN Accelerator. CoRR abs/2409.04976 (2024) - 2023
- [j39]Sumiran Mehra, Gopal Raut, Ribhu Das Purkayastha, Santosh Kumar Vishvakarma, Anton Biasizzo:
An Empirical Evaluation of Enhanced Performance Softmax Function in Deep Learning. IEEE Access 11: 34912-34924 (2023) - [j38]Gunjan Rajput, V. Logashree, Kunika Naresh Biyani, Santosh Kumar Vishvakarma:
Clock Gating-Based Effectual Realization of Stochastic Hyperbolic Tangent Function for Deep Neural Hardware Accelerators. Circuits Syst. Signal Process. 42(10): 5978-6000 (2023) - [j37]Gopal Raut, Jogesh Mukala, Vishal Sharma, Santosh Kumar Vishvakarma:
Designing a Performance-Centric MAC Unit with Pipelined Architecture for DNN Accelerators. Circuits Syst. Signal Process. 42(10): 6089-6115 (2023) - [j36]Vasundhara Trivedi, Khushbu Lalwani, Gopal Raut, Avikshit Khomane, Neha Ashar, Santosh Kumar Vishvakarma:
Hybrid ADDer: A Viable Solution for Efficient Design of MAC in DNNs. Circuits Syst. Signal Process. 42(12): 7596-7614 (2023) - [j35]Kavitha Soundrapandiyan, Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal:
Enabling Energy-Efficient In-Memory Computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array. IEEE J. Emerg. Sel. Topics Circuits Syst. 13(1): 445-455 (2023) - [j34]Ravi Kumar, Rajasekhar Nagulapalli, Santosh Kumar Vishvakarma:
A Novel Bias Circuit Technique to Reduce the PVT Variation of the Ring Oscillator Frequency. J. Circuits Syst. Comput. 32(4): 2350059:1-2350059:10 (2023) - [j33]Ravi Kumar, Pooja Bohara, Krishna Thakur, Santosh Kumar Vishvakarma:
A 5.5-GHz Low-Power Divide-By-8/9 Dual Modulus Prescaler Using Pulse Extension Logic. J. Circuits Syst. Comput. 32(4): 2350068:1-2350068:16 (2023) - [j32]Gopal Raut, Saurabh Karkun, Santosh Kumar Vishvakarma:
An Empirical Approach to Enhance Performance for Scalable CORDIC-Based Deep Neural Networks. ACM Trans. Reconfigurable Technol. Syst. 16(3): 39:1-39:32 (2023) - [c29]Sudheer Vishwakarma, Gopal Raut, Narendra Singh Dhakad, Santosh Kumar Vishvakarma, Dhruva Ghai:
A Configurable Activation Function for Variable Bit-Precision DNN Hardware Accelerators. IFIPIoT (1) 2023: 433-441 - [c28]Mohd Sakib Ansari S, Kavitha S, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma:
Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space Application. VLSID 2023: 104-108 - 2022
- [j31]Harsh Chhajed, Gopal Raut, Narendra Singh Dhakad, Sudheer Vishwakarma, Santosh Kumar Vishvakarma:
BitMAC: Bit-Serial Computation-Based Efficient Multiply-Accumulate Unit for DNN Accelerator. Circuits Syst. Signal Process. 41(4): 2045-2060 (2022) - [j30]Gunjan Rajput, Kunika Naresh Biyani, V. Logashree, Santosh Kumar Vishvakarma:
SCAN: Streamlined Composite Activation Function Unit for Deep Neural Accelerators. Circuits Syst. Signal Process. 41(6): 3465-3486 (2022) - [j29]Gopal Raut, Anton Biasizzo, Narendra Singh Dhakad, Neha Gupta, Gregor Papa, Santosh Kumar Vishvakarma:
Data multiplexed and hardware reused architecture for deep neural network accelerator. Neurocomputing 486: 147-159 (2022) - [j28]Gunjan Rajput, Shashank Agrawal, Gopal Raut, Santosh Kumar Vishvakarma:
An accurate and noninvasive skin cancer screening based on imaging technique. Int. J. Imaging Syst. Technol. 32(1): 354-368 (2022) - [j27]Gunjan Rajput, Shashank Agrawal, Kunika Naresh Biyani, Santosh Kumar Vishvakarma:
Early breast cancer diagnosis using cogent activation function-based deep learning implementation on screened mammograms. Int. J. Imaging Syst. Technol. 32(4): 1101-1118 (2022) - [c27]Varun Bhatnagar, Gopal Raut, Santosh Kumar Vishvakarma:
Loading Effect Free MOS-only Voltage Reference Ladder for ADC in RRAM-crossbar Array. ACM Great Lakes Symposium on VLSI 2022: 199-202 - [c26]Nikhil Rangarajan, Satwik Patnaik, Mohammed Nabeel, Mohammed Ashraf, Shubham Rai, Gopal Raut, Heba Abunahla, Baker Mohammad, Santosh Kumar Vishvakarma, Akash Kumar, Johann Knechtel, Ozgur Sinanoglu:
SCRAMBLE: A Secure and Configurable, Memristor-Based Neuromorphic Hardware Leveraging 3D Architecture. ISVLSI 2022: 308-313 - [c25]S. Kavitha, Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal:
An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array. VDAT 2022: 262-274 - 2021
- [j26]Shubham Rai, Pallab Nath, Ansh Rupani, Santosh Kumar Vishvakarma, Akash Kumar:
A Survey of FPGA Logic Cell Designs in the Light of Emerging Technologies. IEEE Access 9: 91564-91574 (2021) - [j25]Gunjan Rajput, Gopal Raut, Mahesh Chandra, Santosh Kumar Vishvakarma:
VLSI implementation of transcendental function hyperbolic tangent for deep neural network accelerators. Microprocess. Microsystems 84: 104270 (2021) - [j24]Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar:
RECON: Resource-Efficient CORDIC-Based Neuron Architecture. IEEE Open J. Circuits Syst. 2: 170-181 (2021) - [j23]Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar:
Correction to "RECON: Resource-Efficient CORDIC-Based Neuron Architecture". IEEE Open J. Circuits Syst. 2: 292 (2021) - [c24]Jyoti Bhatia, Aveen Dayal, Ajit Jha, Santosh Kumar Vishvakarma, Soumya J., M. B. Srinivas, Phaneendra K. Yalavarthy, Abhinav Kumar, V. Lalitha, Sagar Koorapati, Linga Reddy Cenkeramaddi:
Object Classification Technique for mmWave FMCW Radars using Range-FFT Features. COMSNETS 2021: 111-115 - [c23]Neha Gupta, Nikhil Agrawal, Narendra Singh Dhakad, Ambika Prasad Shah, Santosh Kumar Vishvakarma, Patrick Girard:
Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable Circuits. ACM Great Lakes Symposium on VLSI 2021: 307-312 - 2020
- [j22]Gopal Raut, Ambika Prasad Shah, Vishal Sharma, Gunjan Rajput, Santosh Kumar Vishvakarma:
A 2.4-GS/s Power-Efficient, High-Resolution Reconfigurable Dynamic Comparator for ADC Architecture. Circuits Syst. Signal Process. 39(9): 4681-4694 (2020) - [j21]Ambika Prasad Shah, Santosh Kumar Vishvakarma, Michael Hübner:
Soft Error Hardened Asymmetric 10T SRAM Cell for Aerospace Applications. J. Electron. Test. 36(2): 255-269 (2020) - [j20]Mahesh Kumawat, Abhishek Kumar Upadhyay, Sanjay Sharma, Ravi Kumar, Gaurav Singh, Santosh Kumar Vishvakarma:
An improved current mode logic latch for high-speed applications. Int. J. Commun. Syst. 33(13) (2020) - [j19]Mahesh Kumawat, Mohit Singh Choudhary, Ravi Kumar, Gaurav Singh, Santosh Kumar Vishvakarma:
A Novel CML Latch-Based Wave-Pipelined Asynchronous SerDes Transceiver for Low-Power Application. J. Circuits Syst. Comput. 29(7): 2050110:1-2050110:14 (2020) - [c22]Gopal Raut, Shubham Rai, Santosh Kumar Vishvakarma, Akash Kumar:
A CORDIC Based Configurable Activation Function for ANN Applications. ISVLSI 2020: 78-83
2010 – 2019
- 2019
- [j18]Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Nand Kishor Yadav, Santosh Kumar Vishvakarma, Devesh Dwivedi:
An Auto-Calibrated Sense Amplifier with Offset Prediction Approach for Energy-Efficient SRAM. Circuits Syst. Signal Process. 38(4): 1482-1505 (2019) - [j17]Ambika Prasad Shah, Nandakishor Yadav, Ankur Beohar, Santosh Kumar Vishvakarma:
SUBHDIP: process variations tolerant subthreshold Darlington pair-based NBTI sensor circuit. IET Comput. Digit. Tech. 13(3): 243-249 (2019) - [j16]Sajid Khan, Ambika Prasad Shah, Neha Gupta, Shailesh Singh Chouhan, Jai Gopal Pandey, Santosh Kumar Vishvakarma:
An ultra-low power, reconfigurable, aging resilient RO PUF for IoT applications. Microelectron. J. 92 (2019) - [j15]Prachi Sanvale, Neha Gupta, Vaibhav Neema, Ambika Prasad Shah, Santosh Kumar Vishvakarma:
An improved read-assist energy efficient single ended P-P-N based 10T SRAM cell for wireless sensor network. Microelectron. J. 92 (2019) - [c21]Sajid Khan, Neha Gupta, Abhinav Vishwakarma, Shailesh Singh Chouhan, Jai Gopal Pandey, Santosh Kumar Vishvakarma:
Dual-Edge Triggered Lightweight Implementation of AES for IoT Security. VDAT 2019: 298-307 - [c20]Gopal Raut, Vishal Bhartiy, Gunjan Rajput, Sajid Khan, Ankur Beohar, Santosh Kumar Vishvakarma:
Efficient Low-Precision CORDIC Algorithm for Hardware Implementation of Artificial Neural Network. VDAT 2019: 321-333 - [c19]Sajid Khan, Neha Gupta, Gopal Raut, Gunjan Rajput, Jai Gopal Pandey, Santosh Kumar Vishvakarma:
An Ultra Low Power AES Architecture for IoT. VDAT 2019: 334-344 - [c18]Neha Gupta, Jitesh Prasad, Rana Sagar Kumar, Gunjan Rajput, Santosh Kumar Vishvakarma:
A Robust Low-Power Write-Assist Data-Dependent-Power-Supplied 12T SRAM Cell. VDAT 2019: 630-642 - [c17]Neha Gupta, Tanisha Gupta, Sajid Khan, Abhinav Vishwakarma, Santosh Kumar Vishvakarma:
Low Leakage Highly Stable Robust Ultra Low Power 8T SRAM Cell. VDAT 2019: 643-654 - [c16]Ankur Beohar, Gopal Raut, Gunjan Rajput, Abhinav Vishwakarma, Ambika Prasad Shah, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma:
Compact Spiking Neural Network System with SiGe Based Cylindrical Tunneling Transistor for Low Power Applications. VDAT 2019: 655-663 - [p1]Balwinder Raj, Jeetendra Singh, Santosh Kumar Vishvakarma, Shailesh Singh Chouhan:
IoT-Based Ambient Intelligence Microcontroller for Remote Temperature Monitoring. Guide to Ambient Intelligence in the IoT Environment 2019: 177-200 - [e1]Anirban Sengupta, Sudeb Dasgupta, Virendra Singh, Rohit Sharma, Santosh Kumar Vishvakarma:
VLSI Design and Test - 23rd International Symposium, VDAT 2019, Indore, India, July 4-6, 2019, Revised Selected Papers. Communications in Computer and Information Science 1066, Springer 2019, ISBN 978-981-32-9766-1 [contents] - 2018
- [j14]Pooran Singh, Santosh Kumar Vishvakarma:
Ultra-Low Power High Stability 8T SRAM for Application in Object Tracking System. IEEE Access 6: 2279-2290 (2018) - [j13]S. Mishra, Pandurang S. Londhe, Mohan Santhakumar, Santosh Kumar Vishvakarma, B. M. Patre:
Robust task-space motion control of a mobile manipulator using a nonlinear control with an uncertainty estimator. Comput. Electr. Eng. 67: 729-740 (2018) - [j12]Vishal Sharma, Santosh Kumar Vishvakarma, Shailesh Singh Chouhan, Kari Halonen:
A write-improved low-power 12T SRAM cell for wearable wireless sensor nodes. Int. J. Circuit Theory Appl. 46(12): 2314-2333 (2018) - [j11]Pooran Singh, Bhupendra Singh Reniwal, Vikas Vijayvargiya, V. Sharma, Santosh Kumar Vishvakarma:
Ultra low power-high stability, positive feedback controlled (PFC) 10T SRAM cell for look up table (LUT) design. Integr. 62: 1-13 (2018) - [j10]Ambika Prasad Shah, Nandakishor Yadav, Ankur Beohar, Santosh Kumar Vishvakarma:
An efficient NBTI sensor and compensation circuit for stable and reliable SRAM cells. Microelectron. Reliab. 87: 15-23 (2018) - [c15]Aditya Japa, T. Nagateja, Santosh Kumar Vishvakarma, Palagani Yellappa, Jun Rim Choi, Ramesh Vaddi:
Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities. ISCAS 2018: 1-5 - [c14]Jai Gopal Pandey, Tarun Goel, Mausam Nayak, Chhavi Mitharwal, Sajid Khan, Santosh Kumar Vishvakarma, Abhijit Karmakar, Raj Singh:
A VLSI Architecture for the PRESENT Block Cipher with FPGA and ASIC Implementations. VDAT 2018: 210-220 - [c13]Vishal Sharma, Pranshu Bisht, Abhishek Dalal, Shailesh Singh Chouhan, H. S. Jattana, Santosh Kumar Vishvakarma:
A Write-Improved Half-Select-Free Low-Power 11T Subthreshold SRAM with Double Adjacent Error Correction for FPGA-LUT Design. VDAT 2018: 551-564 - 2017
- [j9]Pooran Singh, Bhupendra Singh Reniwal, Vikas Vijayvargiya, V. Sharma, Santosh Kumar Vishvakarma:
Dynamic Feedback Controlled Static Random Access Memory for Low Power Applications. J. Low Power Electron. 13(1): 47-59 (2017) - [j8]Bhupendra Singh Reniwal, Praneet Bhatia, Santosh Kumar Vishvakarma:
Design and investigation of variability aware sense amplifier for low power, high speed SRAM. Microelectron. J. 59: 22-32 (2017) - [c12]Ambika Prasad Shah, Nandakishor Yadav, Santosh Kumar Vishvakarma:
LISOCHIN: An NBTI Degradation Monitoring Sensor for Reliable CMOS Circuits. VDAT 2017: 441-451 - [c11]Bhupendra Singh Reniwal, P. Singh, Vikas Vijayvargiya, Santosh Kumar Vishvakarma:
A New Sense Amplifier Design with Improved Input Referred Offset Characteristics for Energy-Efficient SRAM. VLSID 2017: 335-340 - 2016
- [j7]C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi:
Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications. Circuits Syst. Signal Process. 35(2): 385-407 (2016) - [j6]Bhupendra Singh Reniwal, Vikas Vijayvargiya, Santosh Kumar Vishvakarma, Devesh Dwivedi:
Ultra-Fast Current Mode Sense Amplifier for Small \(I_{\mathrm{CELL}}\) SRAM in FinFET with Improved Offset Tolerance. Circuits Syst. Signal Process. 35(9): 3066-3085 (2016) - [j5]C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi:
A 20 nm robust single-ended boost-less 7T FinFET sub-threshold SRAM cell under process-voltage-temperature variations. Microelectron. J. 51: 75-88 (2016) - [j4]C. B. Kushwah, Santosh Kumar Vishvakarma:
A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell. IEEE Trans. Very Large Scale Integr. Syst. 24(1): 373-377 (2016) - [c10]Shraddha Thakre, Ankur Beohar, Vikas Vijayvargiya, Nandakishor Yadav, Santosh Kumar Vishvakarma:
Investigation of DC Characteristic on DG-Tunnel FET with High-K Dielectric Using Distinct Device Parameter. iNIS 2016: 124-128 - [c9]Nandakishor Yadav, Ankur Beohar, Santosh Kumar Vishvakarma:
Analysis of Single-Trap-Induced Random Telegraph Noise on Asymmetric High-k Spacer FinFET. iNIS 2016: 264-267 - 2015
- [j3]Dheeraj Sharma, Santosh Kumar Vishvakarma:
Analyses of DC and analog/RF performances for short channel quadruple-gate gate-all-around MOSFET. Microelectron. J. 46(8): 731-739 (2015) - [c8]Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Santosh Kumar Vishvakarma, Devesh Dwivedi:
Dataline Isolated Differential Current Feed/Mode Sense Amplifier for Small Icell SRAM Using FinFET. ACM Great Lakes Symposium on VLSI 2015: 95-98 - [c7]Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal, V. Sharma, C. B. Khuswah, Devesh Dwivedi:
Nanoscale Memory Design for Efficient Computation: Trends, Challenges and Opportunity. iNIS 2015: 29-34 - [c6]Neha Jagwani, Vikas Vijayvargiya, Santosh Kumar Vishvakarma:
Effect of Gate and Channel Engineering on Digital Performance Parameters Using Tied (3T) and Independent (4T) Double Gate MOSFETs. iNIS 2015: 243-247 - [c5]Praneet Bhatia, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma:
An offset-tolerant self-correcting sense amplifier for robust high speed SRAM. VDAT 2015: 1-6 - 2014
- [c4]C. B. Kushwah, Santosh Kumar Vishvakarma:
A sub-threshold eight transistor (8T) SRAM cell design for stability improvement. ICICDT 2014: 1-4 - [c3]C. B. Kushwah, Santosh Kumar Vishvakarma, Devesh Dwivedi:
Single-ended sub-threshold finfet 7T SRAM cell without boosted supply. ICICDT 2014: 1-4 - 2013
- [c2]Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma:
Process Aware Ultra-High-Speed Hybrid Sensing Technique for Low Power Near-Threshold SRAM. VDAT 2013: 1-9 - 2012
- [j2]Dheeraj Sharma, Santosh Kumar Vishvakarma:
Analytical modeling for 3D potential distribution of rectangular gate (RecG) gate-all-around (GAA) MOSFET in subthreshold and strong inversion regions. Microelectron. J. 43(6): 358-363 (2012) - [c1]Chandrabhan Kushwah, Santosh Kumar Vishvakarma:
Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin. VDAT 2012: 139-146 - 2011
- [j1]Santosh Kumar Vishvakarma, V. Komal Kumar, Ashok K. Saxena, Sudeb Dasgupta:
Modeling and estimation of edge direct tunneling current for nanoscale metal gate (Hf/AlNx) symmetric double gate MOSFET. Microelectron. J. 42(5): 688-692 (2011)
Coauthor Index
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
Unpaywalled article links
Add open access links from 
to the list of external document links (if available).
Privacy notice: By enabling the option above, your browser will contact the API of unpaywall.org to load hyperlinks to open access articles. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Unpaywall privacy policy.
Archived links via Wayback Machine
For web page which are no longer available, try to retrieve content from the 
of the Internet Archive (if available).
Privacy notice: By enabling the option above, your browser will contact the API of archive.org to check for archived content of web pages that are no longer available. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Internet Archive privacy policy.
Reference lists
Add a list of references from 
, 
, and 
to record detail pages.
load references from crossref.org and opencitations.net
Privacy notice: By enabling the option above, your browser will contact the APIs of crossref.org, opencitations.net, and semanticscholar.org to load article reference information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the Crossref privacy policy and the OpenCitations privacy policy, as well as the AI2 Privacy Policy covering Semantic Scholar.
Citation data
Add a list of citing articles from and to record detail pages.
load citations from opencitations.net
Privacy notice: By enabling the option above, your browser will contact the API of opencitations.net and semanticscholar.org to load citation information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the OpenCitations privacy policy as well as the AI2 Privacy Policy covering Semantic Scholar.
OpenAlex data
Load additional information about publications from 
.
Privacy notice: By enabling the option above, your browser will contact the API of openalex.org to load additional information. Although we do not have any reason to believe that your call will be tracked, we do not have any control over how the remote server uses your data. So please proceed with care and consider checking the information given by OpenAlex.
last updated on 2024-10-10 22:19 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
