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"Hardware Architecture and FPGA Implementation of Low Latency Turbo Encoder ..."

Meghvern Pathak, Rahul Shrestha (2023)

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DOI: 10.1109/VLSID57277.2023.00016

access: closed

type: Conference or Workshop Paper

metadata version: 2023-04-22

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Meghvern Pathak, Rahul Shrestha:
Hardware Architecture and FPGA Implementation of Low Latency Turbo Encoder for Deep-Space Communication Systems. VLSID 2023: 1-6

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