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Publication search results
found 24 matches
- 2022
- Ke Ma, Xiaopeng Li:
Empirical study of feedback delay in stability analysis for production vehicles with different powertrains. ITSC 2022: 4196-4201 - 2021
- Baba Fayaz D, Sreehari Rao Patri:
Power-efficient voltage up level shifter with low power-delay product. Int. J. Circuit Theory Appl. 49(7): 2158-2169 (2021) - 2019
- Ghasem Pasandi, Raghav Mehta, Massoud Pedram, Shahin Nazarian:
Hybrid Cell Assignment and Sizing for Power, Area, Delay-Product Optimization of SRAM Arrays. IEEE Trans. Circuits Syst. II Express Briefs 66-II(12): 2047-2051 (2019) - Bardia Safaei, Ali Asghar Mohammad Salehi, Maryam Shirbeigi, Amir Mahdi Hosseini Monazzah, Alireza Ejlali:
PEDAL: power-delay product objective function for internet of things applications. SAC 2019: 892-895 - Ghasem Pasandi, Raghav Mehta, Massoud Pedram, Shahin Nazarian:
Hybrid Cell Assignment and Sizing for Power, Area, Delay Product Optimization of SRAM Arrays. CoRR abs/1902.00484 (2019) - 2018
- Huan Minh Vo:
Comparative Study on Power Gating Techniques for Lower Power Delay Product, Smaller Power Loss, Faster Wakeup Time. EAI Endorsed Trans. Ind. Networks Intell. Syst. 5(15): e1 (2018) - 2017
- Pei Liu, Tian Zhao, Feng Liang, Jizhong Zhao, Peilin Jiang:
A power-delay-product efficient and SEU-tolerant latch design. IEICE Electron. Express 14(23): 20170972 (2017) - Shantanu Dutt, Ouwen Shi:
Power-delay product based resource library construction for effective power optimization in HLS. ISQED 2017: 229-236 - 2015
- Aimed Lutfi Elgreatly, Aimed Ahmed Shaaban, El-Sayed M. El-Rabaie:
Enhancing Power Delay Product in DRAMs using resonant tunneling diode buffer. ICM 2015: 230-233 - 2014
- I-Chyn Wey, Yu-Sheng Yang, Bing-Chen Wu, Chien-Chang Peng:
A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design. Microelectron. J. 45(1): 1-13 (2014) - Sachin Maheshwari, Jimit Patel, Sumit K. Nirmalkar, Anu Gupta:
Logical effort based power-delay-product optimization. ICACCI 2014: 565-569 - 2012
- Supriya Aggarwal, Kavita Khare:
Design Techniques Targeting Low-Area-Power-Delay Product in Hyperbolic CORDIC Algorithm. Comput. J. 55(5): 616-628 (2012) - 2011
- Mohammad Ghasemazar, Massoud Pedram:
Optimizing the Power-Delay Product of a Linear Pipeline by Opportunistic Time Borrowing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(10): 1493-1506 (2011) - 2009
- Sasidharan Ekambavanan, Rajesh Garg, Sunil P. Khatri, Krishna R. Narayanan:
Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization. J. Low Power Electron. 5(2): 157-172 (2009) - Anis Uzzaman, Brion L. Keller, Thomas J. Snethen, Kazuhiko Iwasaki, Masayuki Arai:
Automatic Handling of Programmable On-Product Clock Generation (OPCG) Circuitry for Low Power Aware Delay Test. J. Low Power Electron. 5(4): 520-528 (2009) - 2008
- Armin Tajalli, Frank K. Gürkaynak, Yusuf Leblebici, Massimo Alioto, Elizabeth J. Brauer:
Improving the power-delay product in SCL circuits using source follower output stage. ISCAS 2008: 145-148 - 2005
- Myeong-Hoon Oh, Dong-Soo Har:
Low Delay-Power Product Current-Mode Multiple Valued Logic for Delay-Insensitive Data Transfer Mechanism. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(5): 1379-1383 (2005) - Hui Zhang, Pinaki Mazumder:
Design of a new sense amplifier flip-flop with improved power-delay-product. ISCAS (2) 2005: 1262-1265 - 2004
- Amaury Nève, Helmut Schettler, Thomas Ludwig, Denis Flandre:
Power-delay product minimization in high-performance 64-bit carry-select adders. IEEE Trans. Very Large Scale Integr. Syst. 12(3): 235-244 (2004) - Donglai Zhu, Kuldip K. Paliwal:
Product of power spectrum and group delay function for speech recognition. ICASSP (1) 2004: 125-128 - 2003
- Chi-Ming Tsai, Guang-Wan Liao, Rung-Bin Lin:
A Low Power-Delay Product Page-Based Address Bus Coding Method. VLSI Design 2003: 521-526 - 1996
- S. Turgis, Nadine Azémard, Daniel Auvergne:
Design and selection of buffers for minimum power-delay product. ED&TC 1996: 224-229 - 1995
- William A. Chren Jr.:
Low delay-power product CMOS design using one-hot residue coding. ISLPD 1995: 145-150 - 1994
- Jso-Sun Choi, Kwyro Lee:
Design of CMOS tapered buffer for minimum power-delay product. IEEE J. Solid State Circuits 29(9): 1142-1145 (1994)
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