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Publication search results
found 46 matches
- 2023
- Chang Liu, Yan-Jun Wu, Jing-Zheng Wu, Chen Zhao:
A buffer overflow detection and defense method based on RISC-V instruction set extension. Cybersecur. 6(1): 45 (2023) - 2021
- Pavlos Aimoniotis, Christos Sakalis, Magnus Själander, Stefanos Kaxiras:
Reorder Buffer Contention: A Forward Speculative Interference Attack for Speculation Invariant Instructions. IEEE Comput. Archit. Lett. 20(2): 162-165 (2021) - 2020
- Oualid Trabelsi, Laurent Sauvage, Jean-Luc Danger:
Characterization of Electromagnetic Fault Injection on a 32-bit Microcontroller Instruction Buffer. AsianHOST 2020: 1-6 - 2018
- Samira Mirbagher Ajorpaz, Elba Garza, Sangam Jindal, Daniel A. Jiménez:
Exploring Predictive Replacement Policies for Instruction Cache and Branch Target Buffer. ISCA 2018: 519-532 - 2017
- Anoop Bhagyanath, Klaus Schneider:
Exploring the Potential of Instruction-Level Parallelism of Exposed Datapath Architectures with Buffered Processing Units. ACSD 2017: 106-115 - Omayma Matoussi, Frédéric Pétrot:
Modeling instruction cache and instruction buffer for performance estimation of VLIW architectures using native simulation. DATE 2017: 266-269 - 2015
- Muhammad Yasir Qadri, Nadia N. Qadri, Martin Fleury, Klaus D. McDonald-Maier:
Software-Controlled Instruction Prefetch Buffering for Low-End Processors. J. Circuits Syst. Comput. 24(10): 1550161:1-1550161:17 (2015) - 2013
- Jih-Ching Chiu, Kai-Ming Yang, Yu-Liang Chou, Chih-Kang Wu:
A relation-exchanging buffering mechanism for instruction and data streaming. Comput. Electr. Eng. 39(4): 1129-1141 (2013) - Qi Wang, Yingke Gao, Donghui Wang, Tiejun Zhang, Chaohuan Hou:
Design and implementation of a dynamic loop buffer by reusing the instruction buffer. ASICON 2013: 1-4 - 2012
- Hyun-Bum Cho, Ju Hee Choi, Seong-Tea Jhang, Chu-Shik Jhon:
Low Power Instruction Cache with Word Selective Line Buffer. CSE 2012: 215-222 - 2011
- Vladimír Guzma, Teemu Pitkänen, Jarmo Takala:
Effects of loop unrolling and use of instruction buffer on processor energy consumption. SoC 2011: 82-85 - Vladimír Guzma, Teemu Pitkänen, Jarmo Takala:
Instruction buffer with limited control flow and loop nest support. ICSAMOS 2011: 263-269 - 2010
- Jih-Ching Chiu, Kai-Ming Yang:
A Novel instruction stream buffer for VLIW architectures. Comput. Electr. Eng. 36(1): 190-198 (2010) - Jih-Ching Chiu, Yu-Liang Chou, Tseng-Kuei Lin:
The Basic Block Reassembling Instruction Stream Buffer with LWBTB for X86 ISA. J. Inf. Sci. Eng. 26(4): 1273-1288 (2010) - Vladimír Guzma, Teemu Pitkänen, Jarmo Takala:
Reducing instruction memory energy consumption by using Instruction Buffer and after scheduling analysis. SoC 2010: 99-102 - Antonio Artés, Filipa Duarte, Maryam Ashouei, Jos Huisken, José Luis Ayala, David Atienza, Francky Catthoor:
Energy Efficiency Using Loop Buffer based Instruction Memory Organizations. IWIA 2010: 59-67 - 2009
- Francesco Gadaleta, Yves Younan, Bart Jacobs, Wouter Joosen, Erik De Neve, Nils Beosier:
Instruction-level countermeasures against stack-based buffer overflow attacks. VDTS@EuroSys 2009: 7-12 - Weili Li, Lixin Yu:
Efficient line buffer instruction cache scheme with prefetch. ICIS 2009: 132-135 - 2008
- Jih-Ching Chiu, Yu-Liang Chou, Ta-Li Yeh, Tseng-Kuei Lin:
Designs of the basic block reassembling Instruction Stream Buffer for X86 ISA. ACSAC 2008: 1-8 - Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano:
Instruction buffer mode for multi-context Dynamically Reconfigurable Processors. FPL 2008: 215-220 - 2006
- Bramha Allu, Wei Zhang:
Reducing Instruction Translation Look-Aside Buffer Energy Through Compiler-Directed Resizing. J. Low Power Electron. 2(2): 140-147 (2006) - Chi Ta Wu, Ang-Chih Hsieh, TingTing Hwang:
Instruction buffering for nested loops in low-power design. IEEE Trans. Very Large Scale Integr. Syst. 14(7): 780-784 (2006) - Bin-Hua Tein, I-Wei Wu, Chung-Ping Chung:
Instruction Fetch Energy Reduction Using Forward-Branch Bufferable Innermost Loop Buffer. CDES 2006: 91-96 - 2005
- Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Henk Corporaal, Francky Catthoor:
Instruction buffering exploration for low energy embedded processors. J. Embed. Comput. 1(3): 341-351 (2005) - Kashif Ali, Mokhtar Aboelaze, Suprakash Datta:
Reducing Energy in Instruction Caches by Using Multiple Line Buffers with Prediction. ISHPC 2005: 508-521 - 2004
- Christian Panis, Herbert Grünbacher, Jari Nurmi:
A scalable instruction buffer and align unit for xDSPcore. IEEE J. Solid State Circuits 39(7): 1094-1100 (2004) - Tom Vander Aa, Murali Jayapala, Francisco Barat, Geert Deconinck, Rudy Lauwereins, Francky Catthoor, Henk Corporaal:
Instruction buffering exploration for low energy VLIWs with instruction clusters. ASP-DAC 2004: 824-829 - Jingren Zhou, Kenneth A. Ross:
Buffering Database Operations for Enhanced Instruction Cache Performance. SIGMOD Conference 2004: 191-202 - 2003
- Christian Panis, Michael Bramberger, Herbert Grünbacher, Jari Nurmi:
A scaleable instruction buffer for a configurable DSP core. ESSCIRC 2003: 49-52 - Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno:
Reducing instruction fetch energy with backwards branch control information and buffering. ISLPED 2003: 322-325
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