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Publication search results
found 40 matches
- 2023
- Marcos T. Leipnitz, Gabriel L. Nazar:
Constraint-Aware Multi-Technique Approximate High-Level Synthesis for FPGAs. ACM Trans. Reconfigurable Technol. Syst. 16(4): 61:1-61:28 (2023) - 2022
- Koyu Ohata, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
ILP-Based and Heuristic Scheduling Techniques for Variable-Cycle Approximate Functional Units in High-Level Synthesis. Comput. 11(10): 146 (2022) - Antonios Tragoudaras, Pavlos Stoikos, Konstantinos Fanaras, Athanasios Tziouvaras, George Floros, Georgios Dimitriou, Kostas Kolomvatsos, Georgios I. Stamoulis:
Design Space Exploration of a Sparse MobileNetV2 Using High-Level Synthesis and Sparse Matrix Techniques on FPGAs. Sensors 22(12): 4318 (2022) - 2019
- Yu Ting Chen, Jin Hee Kim, Kexin Li, Graham Hoyes, Jason Helge Anderson:
High-Level Synthesis Techniques to Generate Deeply Pipelined Circuits for FPGAs with Registered Routing. FPT 2019: 375-378 - Konstantina Koliogeorgi, Georgios Zervakis, Dimitrios Anagnostos, Nikolaos Zompakis, Kostas Siozios:
Optimizing SVM Classifier Through Approximate and High Level Synthesis Techniques. MOCAST 2019: 1-4 - 2018
- Christian Pilato, Francesco Regazzoni, Ramesh Karri, Siddharth Garg:
TAO: techniques for algorithm-level obfuscation during high-level synthesis. DAC 2018: 155:1-155:6 - 2017
- Jeffrey Goeders, Steven J. E. Wilton:
Signal-Tracing Techniques for In-System FPGA Debugging of High-Level Synthesis Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(1): 83-96 (2017) - Pavan Kumar Bussa, Jeffrey Goeders, Steven J. E. Wilton:
Accelerating in-system FPGA debug of high-level synthesis circuits using incremental compilation techniques. FPL 2017: 1-4 - 2015
- Efstathios Sotiriou-Xanthopoulos, Dionysios Diamantopoulos, George Economakos:
Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures. ARC 2015: 321-330 - Jongsok Choi, Stephen Dean Brown, Jason Helge Anderson:
Resource and memory management techniques for the high-level synthesis of software threads into parallel FPGA hardware. FPT 2015: 152-159 - 2013
- Joshua S. Monson, Michael J. Wirthlin, Brad L. Hutchings:
Optimization techniques for a high level synthesis implementation of the Sobel filter. ReConFig 2013: 1-6 - 2011
- D. S. Harish Ram, M. C. Bhuvaneswari, S. M. Logesh:
A Novel Evolutionary Technique for Multi-objective Power, Area and Delay Optimization in High Level Synthesis of Datapaths. ISVLSI 2011: 290-295 - 2010
- Taemin Kim, Xun Liu:
A global interconnect reduction technique during high level synthesis. ASP-DAC 2010: 695-700 - John Curreri, Greg Stitt, Alan D. George:
High-level synthesis techniques for in-circuit assertion-based verification. IPDPS Workshops 2010: 1-8 - 2009
- Steve Perry:
Model Based Design needs high level synthesis - A collection of high level synthesis techniques to improve productivity and quality of results for model based electronic design. DATE 2009: 1202-1207 - 2008
- Alberto A. Del Barrio, María C. Molina, Jose Manuel Mendias, Esther Andres Perez, Román Hermida:
Restricted Chaining and Fragmentation Techniques in Power Aware High Level Synthesis. DSD 2008: 267-273 - Naghmeh Karimi, Soheil Aminzadeh, Saeed Safari, Zainalabedin Navabi:
A Novel GA-Based High-Level Synthesis Technique to Enhance RT-Level Concurrent Testing. IOLTS 2008: 173-174 - 2007
- Xianwu Xing, Ching-Chuen Jong:
A look-ahead synthesis technique with backtracking for switching activity reduction in low power high-level synthesis. Microelectron. J. 38(4-5): 595-605 (2007) - 2006
- Nobuhiro Doi, Takashi Horiyama, Masaki Nakanishi, Shinji Kimura:
Bit-Length Optimization Method for High-Level Synthesis Based on Non-linear Programming Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3427-3434 (2006) - 2003
- Mahmoud Méribout, Masato Motomura:
A Hierarchical Cost Estimation Technique for High Level Synthesis. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(2): 444-461 (2003) - Alan Mycroft, Richard Sharp:
Higher-level techniques for hardware description and synthesis. Int. J. Softw. Tools Technol. Transf. 4(3): 271-297 (2003) - Saeed Safari, Hadi Esmaeilzadeh, Amir-Hossein Jahangir:
A novel improvement technique for high-level test synthesis. ISCAS (5) 2003: 609-612 - 2002
- Chunhong Chen, Majid Sarrafzadeh:
Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis. DATE 2002: 1016-1020 - 2001
- Sumit Gupta, Nick Savoiu, Sunwoo Kim, Nikil D. Dutt, Rajesh K. Gupta, Alexandru Nicolau:
Speculation Techniques for High Level Synthesis of Control Intensive Designs. DAC 2001: 269-272 - 2000
- Helvio P. Peixoto, Margarida F. Jacome:
A new technique for estimating lower bounds on latency for high level synthesis. ACM Great Lakes Symposium on VLSI 2000: 129-132 - Mohamed Benmohammed, Abdelatif Rahmoune, Polen Kission:
The application of high-level synthesis techniques for the generation of pipelined reprogrammable microcontrollers. ICECS 2000: 993-998 - 1998
- Inki Hong, Darko Kirovski, Kevin T. Kornegay, Miodrag Potkonjak:
High-level synthesis techniques for functional test pattern execution1. Integr. 25(2): 161-180 (1998) - Miguel Miranda, Francky Catthoor, Martin Janssen, Hugo De Man:
High-level address optimization and synthesis techniques for data-transfer-intensive applications. IEEE Trans. Very Large Scale Integr. Syst. 6(4): 677-686 (1998) - Adam Postula, David Abramson, Ziping Fang, Paul Logothetis:
A Comparison of High Level Synthesis and Register Transfer Level Design Techniques for Custom Computing Machines. HICSS (7) 1998: 207-215 - 1997
- Janardhan H. Satyanarayana, Behrouz Nowrouzian:
A New Technique for the High-Level Synthesis of Digit-Serial Digital Filters Based on Genetic Algorithms. J. Circuits Syst. Comput. 7(6): 517-536 (1997)
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