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Publication search results
found 28 matches
- 2014
- Earl E. Swartzlander Jr.:
High-Speed Computer Arithmetic. Computing Handbook, 3rd ed. (1) 2014: 20: 1-28 - 2001
- Haridimos T. Vergos, Dimitris Nikolos, Costas Efstathiou:
High Speed Parallel-Prefix Modulo 2n+1 Adders for Diminished-One Operands. IEEE Symposium on Computer Arithmetic 2001: 211-217 - 1999
- Martin S. Schmookler, Michael Putrino, Anh Mather, Jon Tyler, Huy Van Nguyen, Charles Roth, Mukesh Sharma, Mydung N. Pham, Jeff Lent:
A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension. IEEE Symposium on Computer Arithmetic 1999: 12- - Michael J. Schulte, Kent E. Wires:
High-Speed Inverse Square Roots. IEEE Symposium on Computer Arithmetic 1999: 124- - 1997
- Earl E. Swartzlander Jr.:
High-Speed Computer Arithmetic. The Computer Science and Engineering Handbook 1997: 462-481 - 1995
- Vijay K. Jain, L. Lin:
High-speed double precision computation of nonlinear functions. IEEE Symposium on Computer Arithmetic 1995: 107-114 - Feng Zhou, Peter Kornerup:
High Speed DCT/IDCT Using a Pipelined CORDIC Algorithm. IEEE Symposium on Computer Arithmetic 1995: 180-187 - 1991
- Mayur Mehta, Vijay Parmar, Earl E. Swartzlander Jr.:
High-speed multiplier design using multi-input counter and compressor circuits. IEEE Symposium on Computer Arithmetic 1991: 43-50 - 1990
- Stanislaw J. Piestrak:
Design of High-Speed and Cost-Effective Self-Testing Checkers for Low-Cost Arithmetic Codes. IEEE Trans. Computers 39(3): 360-374 (1990) - 1989
- Jan Fandrianto:
Algorithm for high speed shared radix 8 division and radix 8 square root. IEEE Symposium on Computer Arithmetic 1989: 68-75 - D. L. Fowler, James E. Smith:
An accurate, high speed implementation of division by reciprocal approximation. IEEE Symposium on Computer Arithmetic 1989: 60-67 - 1987
- Jan Fandrianto:
Algorithm for high speed shared radix 4 division and radix 4 square-root. IEEE Symposium on Computer Arithmetic 1987: 73-79 - Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi:
Design of high speed MOS multiplier and divider using redundant binary representation. IEEE Symposium on Computer Arithmetic 1987: 80-86 - 1985
- M. Ohhashi, R. K. Schneider:
High-speed computation of unary functions. IEEE Symposium on Computer Arithmetic 1985: 82-85 - Earl E. Swartzlander Jr., John A. Eldon:
Arithmetic for high speed FFT implementation. IEEE Symposium on Computer Arithmetic 1985: 223-230 - Kenji Taniguchi:
Three dimensional IC's and an application to high speed image processor. IEEE Symposium on Computer Arithmetic 1985: 216-222 - 1983
- Hideaki Kobayashi, Ronald D. Bonnell:
Arithmetic for a high-speed adaptive learning network element. IEEE Symposium on Computer Arithmetic 1983: 164-168 - Stanislaw Majerski:
Square-root algorithms for high-speed digital circuits. IEEE Symposium on Computer Arithmetic 1983: 99-102 - Robert B. Seidensticker:
Continued fractions for high-speed and high-accuracy computer arithmetic. IEEE Symposium on Computer Arithmetic 1983: 184-193 - 1981
- J. B. Gosling, John H. Zurawski, David B. G. Edwards:
A chip-set for a high-speed low-cost floating-point unit. IEEE Symposium on Computer Arithmetic 1981: 50-55 - 1980
- Earl E. Swartzlander Jr., Barry K. Gilbert:
Arithmetic for Ultra-High-Speed Tomography. IEEE Trans. Computers 29(5): 341-353 (1980) - Jan V. Zeman, H. Troy Nagle Jr.:
A High-Speed Microprogrammable Digital Signal Processor Employing Distributed Arithmetic. IEEE Trans. Computers 29(2): 134-144 (1980) - 1979
- Dharma P. Agrawal:
High-Speed Arithmetic Arrays. IEEE Trans. Computers 28(3): 215-224 (1979) - 1978
- Raymond S. Lim:
High-speed multiplication and multiple summand addition. IEEE Symposium on Computer Arithmetic 1978: 149-153 - 1975
- Dharma P. Agrawal:
Optimum array-like structures for high-speed arithmetic. IEEE Symposium on Computer Arithmetic 1975: 208-219 - Arnold Weinberger:
High-speed zero-sum detection. IEEE Symposium on Computer Arithmetic 1975: 200-207 - 1972
- Robert T. Chien, Se June Hong:
Error Correction in High-Speed Arithmetic. IEEE Trans. Computers 21(5): 433-438 (1972) - M. S. Schmookler:
Considerations in the design of a high speed decimal unit. IEEE Symposium on Computer Arithmetic 1972: 1-10
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retrieved on 2024-05-07 14:44 CEST from data curated by the dblp team
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