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ORCIDJerzy Tyszer
- > Home > Persons > Jerzy Tyszer
Publications
- 2015
[j49]Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang:
Isometric Test Data Compression. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 34(11): 1847-1859 (2015)- [j48]Wu-Tung Cheng, Yan Dong, Grady Giles, Yu Huang, Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Scan Test Bandwidth Management for Ultralarge-Scale System-on-Chip Architectures. IEEE Trans. Very Large Scale Integr. Syst. 23(6): 1050-1062 (2015) - 2014
- [j46]Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Erratum to "Test Time Reduction in EDT Bandwidth Management for SoC Designs". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(1): 167 (2014) - [c60]Amit Kumar, Mark Kassab, Elham K. Moghaddam, Nilanjan Mukherjee, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Chen Wang:
Isometric test compression with low toggling activity. ITC 2014: 1-7 - 2013
- [j44]Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Test Time Reduction in EDT Bandwidth Management for SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 32(11): 1776-1786 (2013) - [c58]Jakub Janicki, Jerzy Tyszer, Wu-Tung Cheng, Yu Huang, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Yan Dong, Grady Giles:
EDT bandwidth management - Practical scenarios for large SoC designs. ITC 2013: 1-10 - 2012
- [j43]Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
EDT Bandwidth Management in SoC Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(12): 1894-1907 (2012) - 2011
- [c47]Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski:
EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. ITC 2011: 1-9 - 2010
- [c45]Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer:
Dynamic channel allocation for higher EDT compression in SoC designs. ITC 2010: 265-274 - 2009
- [j36]Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low-Power Scan Operation in Test Compression Environment. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(11): 1742-1755 (2009) - 2008
- [j35]Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab:
X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1): 147-159 (2008) - [c38]Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer:
Low Power Scan Shift and Capture in the EDT Environment. ITC 2008: 1-10 - 2007
- [j33]Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai:
X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Des. Test Comput. 24(5): 476-485 (2007) - 2006
- [c32]Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab:
X-Press Compactor for 1000x Reduction of Test Data. ITC 2006: 1-10 - 2004
- [j28]Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee:
Embedded deterministic test. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(5): 776-792 (2004) - 2003
- [j25]Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian:
Embedded Deterministic Test for Low-Cost Manufacturing. IEEE Des. Test Comput. 20(5): 58-66 (2003) - 2002
- [c20]Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian:
Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC 2002: 301-310 - 1995
- [c8]Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer:
Software Accelerated Functional Fault Simulation for Data-Path Architectures. DAC 1995: 333-338 - [c6]Mark Kassab, Janusz Rajski, Jerzy Tyszer:
Hierarchical Functional-Fault Simulation for High-Level Synthesis. ITC 1995: 596-605
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