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 | 2011 | |
|---|---|---|
| j10 |      | Shu-Yi Wong, Chunhong Chen: Power efficient multi-stage CMOS rectifier design for UHF RFID tags. Integration 44(3): 242-255 (2011) |
| j9 | | Shu-Yi Wong, Chunhong Chen, Q. M. Jonathan Wu: Low Power Chien Search for BCH Decoder Using RT-Level Power Management. IEEE Trans. VLSI Syst. 19(2): 338-341 (2011) |
| 2009 | ||
| j8 | | Chunni Dai, Meng Yao, Zhujie Xie, Chunhong Chen, Jingao Liu: Parameter optimization for growth model of greenhouse crop using genetic algorithms. Appl. Soft Comput. 9(1): 13-19 (2009) |
| c19 | | Shu-Yi Wong, Chunhong Chen, Q. M. Jonathan Wu: Power-management-based Chien search for low power BCH decoder. ISLPED 2009: 299-302 |
| 2008 | ||
| c18 | | Venketeshwaran Puthucode, Chunhong Chen: An experimental study on multi-island structures for single-electron tunneling based threshold logic. ISCAS 2008: 600-603 |
| c17 | | Mohammed Berhea, Chunhong Chen, Q. M. Jonathan Wu: Protocol-level performance analysis for anti-collision protocols in RFID systems. ISCAS 2008: 1008-1011 |
| 2007 | ||
| c16 | | Shun Li, Feng Zhou, Chunhong Chen, Hua Chen, Yipin Wu: Quasi-Static Energy Recovery Logic with Single Power-Clock Supply. ISCAS 2007: 2124-2127 |
| 2006 | ||
| c15 | | Yanjie Mao, Chunhong Chen: Performance Evaluation and Optimization of Full Adders with Single-Electron Technology. CCECE 2006: 2136-2139 |
| c14 | | Jialin Mi, Chunhong Chen, H. K. Kwan: Power-oriented delay budgeting for combinational circuits. ISCAS 2006 |
| c13 | | Jialin Mi, Chunhong Chen: Finite State Machine Implementation with Single-Electron Tunneling Technology. ISVLSI 2006: 237-241 |
| c12 | | Jialin Mi, Chunhong Chen: Power-Oriented Delay Budgeting for Combinational Circuits. ISVLSI 2006: 361-366 |
| 2005 | ||
| j7 | | Chunhong Chen, Jiang Zhao, Majid Ahmadi: A Novel State Encoding Algorithm for Low Power Implementation. Journal of Circuits, Systems, and Computers 14(3): 597-604 (2005) |
| 2004 | ||
| j6 |  | Ankur Srivastava, Ryan Kastner, Chunhong Chen, Majid Sarrafzadeh: Timing driven gate duplication. IEEE Trans. VLSI Syst. 12(1): 42-51 (2004) |
| c11 | | Feng Zhou, Chunhong Chen, Dawei Jin, Chenling Huang, Hao Min: Evaluating and optimizing power consumption of anti-collision protocols for applications in RFID systems. ISLPED 2004: 357-362 |
| 2003 | ||
| c10 | | Chunhong Chen, Jiang Zhao, Majid Ahmadi: A semi-Gray encoding algorithm for low-power state assignment. ISCAS (5) 2003: 389-392 |
| 2002 | ||
| j5 | | Chunhong Chen, Elaheh Bozorgzadeh, Ankur Srivastava, Majid Sarrafzadeh: Budget Management with Applications. Algorithmica 34(3): 261-275 (2002) |
| j4 | | Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh: Predicting potential performance for digital circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 21(3): 253-262 (2002) |
| j3 | | Chunhong Chen, Jiang Zhao, Majid Ahmadi: Probability-based approach to rectilinear Steiner tree problems. IEEE Trans. VLSI Syst. 10(6): 836-843 (2002) |
| c9 | | Chunhong Chen, Majid Sarrafzadeh: Power-Manageable Scheduling Technique for Control Dominated High-Level Synthesis. DATE 2002: 1016-1020 |
| c8 | | Chunhong Chen, Changjun Kang, Majid Sarrafzadeh: Activity-sensitive clock tree construction for low power. ISLPED 2002: 279-282 |
| c7 | | |
| c6 | | |
| 2001 | ||
| j2 | | Amir H. Farrahi, Chunhong Chen, Ankur Srivastava, Gustavo E. Téllez, Majid Sarrafzadeh: Activity-driven clock design. IEEE Trans. on CAD of Integrated Circuits and Systems 20(6): 705-714 (2001) |
| j1 | | Chunhong Chen, Ankur Srivastava, Majid Sarrafzadeh: On gate level power optimization using dual-supply voltages. IEEE Trans. VLSI Syst. 9(5): 616-629 (2001) |
| c5 | | Ankur Srivastava, Chunhong Chen, Majid Sarrafzadeh: Timing driven gate duplication in technology independent phase. ASP-DAC 2001: 577-582 |
| 2000 | ||
| c4 | | Chunhong Chen, Majid Sarrafzadeh: Power reduction by simultaneous voltage scaling and gate sizing. ASP-DAC 2000: 333-338 |
| c3 | | Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh: Potential Slack: An Effective Metric of Combinational Circuit Performance. ICCAD 2000: 198-201 |
| 1999 | ||
| c2 | | Chunhong Chen, Majid Sarrafzadeh: Provably good algorithm for low power consumption with dual supply voltages. ICCAD 1999: 76-79 |
| c1 | | Chunhong Chen, Majid Sarrafzadeh: An Effective Algorithm for Gate-Level Power-Delay Tradeoff Using Two Voltages. ICCD 1999: 222- |
Colors in the list of coauthors
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