Volume 34, Number 1, January 1985

• 
  David W. Matula, Peter Kornerup: Finite Precision Rational Arithmetic Slash Number Systems. 3-18
• 
  Craig S. Holt, James E. Smith: Self-Diagnosis in Distributed Systems. 19-32
• 
  Dhiraj K. Paradhan: Fault-Tolerant Multiprocessor Link and Bus Network Architectures. 33-45, (Correction: IEEE Transactions on Computers 35(1): 94 (1986))
• 
  Cauligi S. Raghavendra, Mario Gerla, Algirdas Avizienis: Reliable Loop Topologies for Large Local Computer Networks. 46-55
• 
  Wei C. Yen, David W. L. Yen, King-sun Fu: Data Coherence Problem in a Multicache System. 56-65
• 
  Guo-Jie Li, Benjamin W. Wah: The Design of Optimal Systolic Arrays. 66-77

• 
  Jerry H. Tucker, Moiez A. Tapia, A. Wayne Bennett: Boolean Integral Calculus for Digital Systems. 78-81
• 
  Thomas Siegenthaler: Decrypting a Class of Stream Ciphers Using Ciphertext Only. 81-85
• 
  Fabio Somenzi, Silvano Gai, Marco Mezzalama, Paolo Prinetto: Testing Strategy and Technique for Macro-Based Circuits. 85-90
• 
  Miguel Ríos, Nicolas D. Georganas: A Hybrid Multiple-Access Protocol for Data and Voice-Packet Over Local Area Networks. 90-94
• 
  Tsukasa Kawaoka, Yoshikane Takahashi: Test Procedure Optimization for Layered Protocol Implementations. 94-97
• 
  Eike Best, Flaviu Cristian: Comments on "Self-Stabilizing Programs: The Fault-Tolerant Capability of Self-Checking Programs". 97-98

Volume 34, Number 2, February 1985

• 
  Hector Garcia-Molina, Jack Kent: Evaluating Response Time in a Faulty Distributed Computing System. 101-109
• 
  Christos A. Papachristou, Narendar B. Sahgal: An Improved Method for Detecting Functional Faults in Semiconductor Random Access Memories. 110-116
• 
  John A. Stankovic: An Application of Bayesian Decision Theory to Decentralized Control of Job Scheduling. 117-130
• 
  Tsutomu Sasao: An Algorithm to Derive the Complement of a Binary Function with Multiple-Valued Inputs. 131-140
• 
  Nikitas J. Dimopoulos: On the Structure of the Homogeneous Multiprocessor. 141-150
• 
  Mikhail J. Atallah, S. Rao Kosaraju: A Generalized Dictionary Machine for VLSI. 151-155
• 
  Maria Calzarossa, Giuseppe Serazzi: A Characterization of the Variation in Time of Workload Arrival Patterns. 156-162
• 
  Vijay C. Jaswa, Charles E. Thomas, John T. Pedicone: CPAC - Concurrent Processor Architecture for Control. 163-169

• 
  E. O. Nwachukwu: Address Generation in an Array Processor. 170-173
• 
  Mauricio Arango, Hussein G. Badr, David Gelernter: Staged Circuit Switching. 174-180
• 
  Manoj Kumar, Daniel M. Dias, J. Robert Jump: Switching Strategies in Shuffle-Exchange Packet-Switched Networks. 180-186
• 
  Bhabani P. Sinha, Bhargab B. Bhattacharya: On the Numerical Complexity of Short-Circuit Faults in Logic Networks. 186-190
• 
  Okan K. Ersoy: Semisystolic Array Implementation of Circular, Skew Circular, and; Linear Convolutions. 190-196

Volume 34, Number 3, March 1985

• 
  Chien-Chung Shen, Wen-Hsiang Tsai: A Graph Matching Approach to Optimal Task Assignment in Distributed Computing Systems Using a Minimax Criterion. 197-203
• 
  Yung-Terng Wang, Robert J. T. Morris: Load Sharing in Distributed Systems. 204-217
• 
  Eugene E. Lindstrom, Jeffrey Scott Vitter: The Design and Analysis of BucketSort for Bubble Memory Secondary Storage. 218-233
• 
  James E. Smith, James R. Goodman: Instruction Cache Replacement Policies and Organizations. 234-241
• 
  Michael J. Flynn, John D. Johnson, Scott P. Wakefield: On Instruction Sets and Their Formats. 242-254
• 
  Dharma P. Agrawal, Ja-Song Leu: Dynamic Accessibility Testing and Path Length Optimization of Multistage Interconnection Networks. 255-266
• 
  Makoto Imase, Terunao Soneoka, Keiji Okada: Connectivity of Regular Directed Graphs with Small Diameters. 267-273
• 
  Danny C. Sorensen: Analysis of Pairwise Pivoting in Gaussian Elimination. 274-278

• 
  Laxmi N. Bhuyan: An Analysis of Processor-Memory Interconnection Networks. 279-283
• 
  Kewal K. Saluja, Kozo Kinoshita: Test Pattern Generation for API Faults in RAM. 284-287
• 
  Thomas H. Spencer, Jacob Savir: Layout Influences Testability. 287-290
• 
  Kenneth R. Sloan Jr.: Comments on "A Computer Algorithm for Calculating the Product AB Modulo M". 290-292

Volume 34, Number 4, April 1985

• 
  Howard B. Demuth: Electronic Data Sorting. 296-310
• 
  Eric Dittert, Michael J. O'Donnell: Lower Bounds for Sorting with Realistic Instruction Sets. 311-317, (Correction: IEEE Transactions on Computers 35(10): 932 (1986))
• 
  Heikki Mannila: Measures of Presortedness and Optimal Sorting Algorithms. 318-325
• 
  Larry Rudolph: A Robust Sorting Network. 326-336
• 
  Gianfranco Bilardi, Franco P. Preparata: A Minimum Area VLSI Network for O(log n) Time Sorting. 336-343
• 
  Frank Thomson Leighton: Tight Bounds on the Complexity of Parallel Sorting. 344-354
• 
  Alan R. Siegel: Minimum Storage Sorting Networks. 355-361

• 
  Lutz Michael Wegner: Quicksort for Equal Keys. 362-367
• 
  Philip J. Janus, Edmund A. Lamagna: An Adaptive Method for Unknown Distributions in Distributive Partitioned Sorting. 367-372
• 
  Doron Rotem, Nicola Santoro, Jeffrey B. Sidney: Distributed Sorting. 372-376
• 
  Shmuel Zaks: Optimal Distributed Algorithms for Sorting and Ranking. 376-379
• 
  Robert Michael Owens, Joseph JáJá: Parallel Sorting with Serial Momories. 379-383
• 
  Sai Choi Kwan, Jean-Loup Baer: The I/O Performance of Multiway Mergesort and Tag Sort. 383-387
• 
  C. M. McCulloch: Why Merge? - An Examination of Disk Sorting Strategy. 387-391

Volume 34, Number 5, May 1985

• 
  Howard M. Shao, Trieu-Kien Truong, Leslie J. Deutsch, Joseph H. Yuen, Irving S. Reed: A VLSI Design of a Pipeline Reed-Solomon Decoder. 393-403
• 
  Lionel M. Ni, Kai Hwang: Vector-Reduction Techniques for Arithmetic Pipelines. 404-411
• 
  Kyungsook Y. Lee: On the Rearrangeability of 2(log₂N) - 1 Stage Permutation Networks. 412-425
• 
  Sunil K. Jain, Vishwani D. Agrawal: Modeling and Test Generation Algorithms for MOS Circuits. 426-433, (Correction: IEEE Transactions on Computers 34(7): 680 (1985))
• 
  Dhiraj K. Pradhan: Dynamically Restructurable Fault-Tolerant Processor Network Architectures. 434-447
• 
  Frank Thomson Leighton, Charles E. Leiserson: Wafer-Scale Integration of Systolic Arrays. 448-461

• 
  Hung-Chang Du: On the Performance of Synchronous Multiprocessors. 462-472
• 
  Hartmut Schmeck, Heiko Schröder: Dictionary Machines for Different Models of VLSI. 472-475
• 
  Jeffrey H. Lang, Charles A. Zukowski, Richard O. LaMaire, Chae H. An: Integrated-Circuit Logarithmic Arithmetic Units. 475-483
• 
  Sunil Ashtaputre, Carla D. Savage: Systolic Arrays with Embedded Tree Structures for Connectivity Problems. 483-484
• 
  P. S. Moharir: Extending the Scope of Golub's Method Beyond Complex Multiplication. 484-487

Volume 34, Number 6, June 1985

• 
  Wesley W. Chu, Joseph Hellerstein: The Exclusive-Writer Approach to Updating Replicated Files in Distributed Processing Systems. 489-500
• 
  Harry A. G. Wijshoff, Jan van Leeuwen: The Structure of Periodic Storage Schemes for Parallel Memories. 501-505
• 
  Jacques Lenfant: A Versatile Mechanism to Move Data in an Array Processor. 506-522
• 
  Ming Huei Young, Saburo Muroga: Symmetric Minimal Covering Problem and Minimal PLA's with Symmetric Variables. 523-541

• 
  Vladimir Cherkassky, Miroslaw Malek: On Permuting Properties of Regular Rectangular SW-Banyans. 542-546
• 
  M. Ashraf Chughtai: Complete Binary Spanning Trees of the Eight Nearest Neighbor Array. 547-549
• 
  Janusz Rajski, Jerzy Tyszer: Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays. 549-553
• 
  Shiyi Xu, Stephen Y. H. Su: Detecting I/O and Internal Feedback Bridging Faults. 553-557
• 
  Larry A. Dunning: SEC-BED-DED Codes for Error Control in Byte-Organized Memory Systems. 557-562
• 
  Martin Cohn: Counting Sequences with Large Local Distance. 562-565
• 
  Marc Davio, Christian Ronse: Insertion Networks. 565-570
• 
  Peter M. Fenwick: Some Aspects of the Dynamic Behavior of Hierarchical Memories. 570-573
• 
  Fred J. Taylor, G. Papadourakis, Alexander Skavantzos, Thanos Stouraitis: A Radix-4FFT Using Complex RNS Arithmetic. 573-576
• 
  Stanislav Zák, Kai Hwang: Polynomial Division on Systolic Arrays. 577-578
• 
  Arnold L. Rosenberg: A Hypergraph Model for Fault-Tolerant VLSI Processor Arrays. 578-584

Volume 34, Number 7, July 1985

• 
  Yang-Chang Hong: Efficient Computing of Relational Algebraic Primitives in a Database Machine Architecture. 588-595
• 
  Nikolaos Gaitanis: Totally Self-Checking Checkers for Low-Cost Arithmetic Codes. 596-601
• 
  John McGough, Mark Smotherman, Kishor S. Trivedi: The Conservativeness of Reliability Estimates Based on Instantaneous Coverage. 602-609
• 
  Waldo C. Kabat, Anthony S. Wojcik: Automated Synthesis of Combinational Logic Using Theorem-Proving Techniques. 610-632
• 
  Zvi Rosberg: Process Scheduling in a Computer System. 633-645
• 
  Thu Van Vu: Efficient Implementations of the Chinese Remainder Theorem for Sign Detection and Residue Decoding. 646-651

• 
  Hans-Werner Lang, Manfred Schimmler, Hartmut Schmeck, Heiko Schröder: Systolic Sorting on a Mesh-Connected Network. 652-658
• 
  Miron Abramovici, Premachandran R. Menon: A Practical Approach to Fault Simulation and Test Generation for Bridging Faults. 658-663
• 
  Mikhail J. Atallah: On Symmetry Detection. 663-666
• 
  Merav Chlamtac, Itzchak Harary: The Shift X Parity Watch Algorithm for Raster Scan Displays. 666-673
• 
  Heggere S. Ranganath, S. G. Shiva: Correlation of Adjacent Pixels for Multiple Image Registration. 674-677
• 
  Lois Wright Hawkes: A Regular Fault-Tolerant Architecture for Interconnection Networks. 677-680

Volume 34, Number 8, August 1985

• 
  Hao-Yung Lo, Yoshinao Aoki: Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array. 681-691
• 
  David B. Aspinwall, Yale N. Patt: Retrofitting the VAX-11/780 Microarchitecture for IEEE Floating Point Arithmetic - Implementation Issues, Measurements, and Analysis. 692-708
• 
  Charles C. Wang, Trieu-Kien Truong, Howard M. Shao, Leslie J. Deutsch, Jim K. Omura, Irving S. Reed: VLSI Architectures for Computing Multiplications and Inverses in GF(2^m). 709-717
• 
  Anton T. Dahbura, Gerald M. Masson, Che-Liang Yang: Self-Implicating Structures for Diagnosable Systems. 718-723
• 
  Stanislaw Majerski: Square-Rooting Algorithms for High-Speed Digital Circuits. 724-733
• 
  Allan L. Fisher, H. T. Kung: Synchronizing Large VLSI Processor Arrays. 734-740

• 
  R. Gnanasekaran: A Fast-Serial-Parallel Binary Multiplier. 741-744
• 
  Bohdan Smilauer: General Model for Memory Interference in Mulitprocessors and Mean Value Analysis. 744-751
• 
  C. Mani Krishna, Kang G. Shin, Ricky W. Butler: Ensuring Fault Tolerance of Phase-Locked Clocks. 752-756
• 
  George Marsaglia: Note on a Proposed Test for Random Number Generators. 756-758
• 
  Nikolaos Gaitanis: A Totally Self-Chicking Error Indicator. 758-761
• 
  Vijay Pitchumani, Edward P. Stabler: Verification of Register Transfer Level Parallel Control Sequences. 761-765
• 
  Nam Sung Woo, Ashok K. Agrawala: A Symmetric Tree Structure Interconnection Network and its Message Traffic. 765-769
• 
  Gunnar E. Carlsson, J. E. Cruthirds, Harlan B. Sexton, C. G. Wright: Interconnection Networks Based on a Generalization of Cube-Connected Cycles. 769-772
• 
  A. Yavuz Oruç, M. Yaman Oruç, Norman Balabanian: Reconfiguration Alfoithms for Interconnection Networks. 773-776

Volume 34, Number 9, September 1985

• 
  Abdol-Hossein Esfahanian, S. Louis Hakimi: Fault-Tolerant Routing in DeBruijn Communication Networks. 777-788
• 
  Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima: High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree. 789-796
• 
  Stephen J. MacKinnon, Peter D. Taylor, Henk Meijer, Selim G. Akl: An Optimal Algorithm for Assigning Cryptographic Keys to Control Access in a Hierarchy. 797-802
• 
  Subhash C. Kak: Encryption and Error-Correction Coding Using D Sequences. 803-809
• 
  Vijay S. Iyengar, Larry L. Kinney: Concurrent Fault Detection in Microprogrammed Control Units. 810-821
• 
  James H. Applegate, Michael R. Douglas, Yekta Gürsel, Peter Hunter, Charles L. Seitz, Gerald J. Sussman: A Digital Orrery. 822-831
• 
  Donna J. Quammen, John P. Kearns, Mary Lou Soffa: Efficient Storage Management for Temporary Values in Concurrent Programming Languages. 832-840
• 
  Arun K. Somani, Vinod K. Agarwal: An Efficient Unsorted VLSI Dictionary Machine. 841-852

• 
  Ding-Zhu Du, D. Frank Hsu, Frank K. Hwang: Doubly Linked Ring Networks. 853-855
• 
  David Lee: Comparator with Completion Signal. 855-857
• 
  Jean-Michel Muller: Discrete Basis and Computation of Elementary Functions. 857-862
• 
  Keith J. Stelzer, Michael A. Gordon: Implementation of a Constrained Regularization Program (CONTIN) on a Desktop Computer. 862-863
• 
  J. W. Wong, Mostafa H. Ammar: Analysis of Broadcast Delivery in a Videotex System. 863-866
• 
  Shuo-Yen Robert Li: Fast Constant Division Routines. 866-869
• 
  Henryk Krawczyk, Marek Kubale: An Approximation Algorithm for Diagnostic Test Scheduling in Multicomputer Systems. 869-872

Volume 34, Number 10, October 1985

• 
  Daniel A. Reed, Merrell L. Patrick: Iterative Solution of Large, Sparse Linear Systems on a Static Data Flow Architecture: Performance Studies. 874-880
• 
  Paul Hudak, Benjamin Goldberg: Distributed Execution of Functional Programs Using Serial Combinators. 881-891
• 
  Charles E. Leiserson: Fat-Trees: Universal Networks for Hardware-Efficient Supercomputing. 892-901
• 
  Nathaniel J. Davis IV, William Tsun-Yuk Hsu, Howard Jay Siegel: Fault Location Techniques for Distributed Control Interconnection Networks. 902-910
• 
  Jim A. Crammond: A Comparative Study of Unification Algorithms for OR-Parallel Execution of Logic Languages. 911-917
• 
  Chita R. Das, Laxmi N. Bhuyan: Bandwidth Availability of Multiple-Bus Multiprocessors. 918-926
• 
  Gyungho Lee, Clyde P. Kruskal, David J. Kuck: An Empirical Study of Automatic Restructuring of Nonnumerical Programs for Parallel Processors. 927-933
• 
  Trevor N. Mudge, Humoud B. Al-Sadoun: A Semi-Markov Model for the Performance of Multiple-Bus Systems. 934-942
• 
  Gregory F. Pfister, V. Alan Norton: "Hot Spot" Contention and Combining in Multistage Interconnection Networks. 943-948
• 
  Wilfried Oed, Otto Lange: On the Effective Bandwidth of Interleaved Memories in Vector Processor Systems. 949-957

• 
  A. Yavuz Oruç, M. Yaman Oruç: On Testing Isomorphism of Permutation Networks. 958-962
• 
  Ten-Hwang Lai, Alan P. Sprague: Performance of Parallel Branch-and Bound Algorithms. 962-964
• 
  Clyde P. Kruskal, Larry Rudolph, Marc Snir: The Power of Parallel Prefix. 965-968
• 
  Michel Dubois: A Cache-Based Multiprocessor with High Efficiency. 968-972

Volume 34, Number 11, November 1985

• 
  Jeanette Tyler McCall, Joseph G. Tront, F. Gail Gray, Robert M. Haralick, William M. McCormack: Parallel Computer Architectures and Problem Solving Strategies for the Consistent Labeling Problem. 973-980
• 
  Siamak Arya: An Optimal Instruction-Scheduling Model for a Class of Vector Processors. 981-995
• 
  Rudi Klatte, Christian P. Ullrich, Jürgen Wolff von Gudenberg: Arithmetic Specification for Scientific Computation in ADA. 996-1005
• 
  Wayne M. Loucks, V. Carl Hamacher, Bruno R. Preiss, Luke Wong: Short-Packet Transfer Performance in Local Area Ring Networks. 1006-1014
• 
  Ghassan Z. Qadah, Keki B. Irani: A Database Machine for Very Large Relational Databases. 1015-1025
• 
  Bella Bose, Der Jei Lin: Systematic Unidirectional Error-Detecting Codes. 1026-1032
• 
  José A. B. Fortes, C. S. Raghavendra: Gracefully Degradable Processor Arrays. 1033-1044
• 
  Krishna Kant: Finding Interferences Between Rectangular Paths. 1045-1049
• 
  Ryosaku Shimada, Yoshiteru Ohkura, Jun-Ichi Aoe: Nonbinary Arithmetic AN Codes Using Odd Radix Expressions. 1050-1056

• 
  Nripendra N. Biswas: On Bit Steering in the Minimization of the Control Memory of Microprogrammed Processors. 1057-1061
• 
  James H. Graham, Thaddeus F. Kadela: Parallel Algorithms and Architectures for Optimal State Estimation. 1061-1068
• 
  John H. Wensley: Further Comments on "The Reliability of Periodically Repaired n-1/n Parallel Redundant Systems". 1068

Volume 34, Number 12, December 1985

• 
  Jean-Luc Gaudiot, Rex W. Vedder, George K. Tucker, Dennis Finn, Michael L. Campbell: A Distributed VLSI Architecture for Efficient Signal and Data Processing. 1072-1087
• 
  Kang G. Shin, Jyh-Charn Liu: A Cost-Effective Multistage Interconnection Network with Network Overlapping and Memory Interleaving. 1088-1101
• 
  Daniel Hoffman: The Trace Specification of Communications Protocols. 1102-1113
• 
  Thomas J. LeBlanc, Stuart A. Friedberg: HPC: A Model of Structure and Change in Distributed Systems. 1114-1129
• 
  John A. Stankovic, Krithi Ramamritham, Shengchang Cheng: Evaluation of a Flexible Task Scheduling Algorithm for Distributed Hard Real-Time Systems. 1130-1143
• 
  Benjamin W. Wah, Jie-Yong Juang: Resource Scheduling for Local Computer Systems with a Multiaccess Network. 1144-1157
• 
  Sunil K. Sarin, Barbara T. Blaustein, Charles W. Kaufman: System Architecture for Partition-Tolerant Distributed Databases. 1158-1163
• 
  Bernd W. Meister, Philippe A. Janson, Liba Svobodova: Connection-Oriented Versus Connectionless Protocols: A Performance Study. 1164-1173

• 
  Willy Zwaenepoel: Implementation and Performance of Pipes in the V-System. 1174-1185
• 
  Miron Livny, Udi Manber: Distributed Computation Via Active Messages. 1185-1190
• 
  F. Warren Burton: Speculative Computation, Parallelism, and Functional Programming. 1190-1193

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