ICSAMOS 2010:
Samos,
Greece
Fadi J. Kurdahi, Jarmo Takala (Eds.):
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS 2010), Samos, Greece, July 19-22, 2010.
IEEE 2010, ISBN 978-1-4244-7937-5 
Keynotes
Simulation and Modeling
Network Processing
- John McGlone, Roger Woods, Alan J. Marshall, Michaela Blott:
Design of a flexible high-speed FPGA-based flow monitor for next generation networks.
37-44
- Konstantin Septinus, Peter Pirsch, Holger Blume, Ulrich Mayer:
A fully programmable FSM-based Processing Engine for Gigabytes/s header parsing.
45-54
- Damon Fenacci, Björn Franke:
Empirical evaluation of data transformations for network infrastructure applications.
55-62
- Amin El Mrabti, Frédéric Rousseau, Frédéric Pétrot, Jérôme Martin, Romain Lemaire, Emmanuel Vaumorin:
Design environment for the support of configurable Network Interfaces in NoC-based platforms.
63-70
Image and Video Processing
- Muhammad Nadeem, Stephan Wong, Georgi Kuzmanov:
An efficient realization of forward integer transform in H.264/AVC intra-frame encoder.
71-78
- Tero Rintaluoma, Olli Silvén:
SIMD performance in software based mobile video coding.
79-85
- Tim Drijvers, Carlos A. Alba Pinto, Henk Corporaal, Bart Mesman, Gert-Jan van den Braak:
Fast Huffman decoding by exploiting data level parallelism.
86-92
- Christian Banz, Sebastian Hesselbarth, Holger Flatt, Holger Blume, Peter Pirsch:
Real-time stereo vision system using semi-global matching disparity estimation: Architecture and FPGA-implementation.
93-101
System-Level Design
Profiling and Analysis
MP-SoC Programming
Network-On-Chip Interconnects
- N. Thambi Prashank, M. Prasadarao, Avinaba Dutta, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
Enhancements for variable N-point streaming FFT/IFFT on REDEFINE, a runtime reconfigurable architecture.
178-184
- Radu Stefan, Jason de Windt, Kees G. W. Goossens:
On-chip network interfaces supporting automatic burst write creation, posted writes and read prefetch.
185-192
- Debora Matos, Caroline Concatto, Anelise Kologeski, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Márcio Eduardo Kreutz:
Monitor-adapter coupling for NOC performance tuning.
193-199
Compiler Techniques
- Gert-Jan van den Braak, Bart Mesman, Henk Corporaal:
Compile-time GPU memory access optimizations.
200-207
- Xiaoyan Jia, Gerhard Fettweis:
Code generation for a novel STA architecture by using post-processing backend.
208-215
- Jens Huthmann, Peter Müller, Florian Stock, Dietmar Hildenbrand, Andreas Koch:
Accelerating high-level engineering computations by automatic compilation of Geometric Algebra to hardware accelerators.
216-222
- Pekka Jääskeläinen, Carlos S. de La Lama, Pablo Huerta, Jarmo Takala:
OpenCL-based design methodology for application-specific processors.
223-230
Micro-Architecture
- Anurag Negi, M. M. Waliullah, Per Stenström:
LV*: A low complexity lazy versioning HTM infrastructure.
231-240
- Catalin Bogdan Ciobanu, Georgi Kuzmanov, Georgi Gaydadjiev, Alex Ramírez:
A Polymorphic Register File for matrix operations.
241-249
- Felipe Cabarcas, Alejandro Rico, Yoav Etsion, Alex Ramírez:
Interleaving granularity on high bandwidth memory architecture for CMPs.
250-257
- Per Karlström, Wenbiao Zhou, Dake Liu:
Automatic port and bus sizing in NoGap.
258-264
Design Space Exploration
Special Session on Software Defined Radio (SDR) and Cognitive Radio (CR)
- John Glossner:
Special session on software defined radio (SDR) and Cognitive Radio (CR).
292
- Teemu Nylanden, Janne Janhunen, Olli Silvén, Markku J. Juntti:
A GPU implementation for two MIMO-OFDM detectors.
293-300
- Murugappan Senthilvelan, Javier Hormigo, Joon Hwa Chun, Mihai Sima, Daniel Iancu, Michael J. Schulte, John Glossner:
CORDIC-based LMMSE equalizer for Software Defined Radio.
301-308
- Peter Westermann, Hartmut Schröder:
On the scalability of SIMD processing for software defined radio algorithms.
309-317
- Jeroen Declerck, Praveen Raghavan, Frederik Naessens, Tom Vander Aa, Lieven Hollevoet, Antoine Dejonghe, Liesbet Van der Perre:
SDR platform for 802.11n and 3-GPP LTE.
318-323
- Sao-Jie Chen, Pao-Ann Hsiung, Chu Yu, Mao-Hsu Yen, Sakir Sezer, Michael J. Schulte, Yu Hen Hu:
ARAL-CR: An adaptive reasoning and learning cognitive radio platform.
324-331
Special Session on Multicore Architectures for Embedded Systems
- Luigi Carro, Stephan Wong:
Special session on multicore architectures for embedded systems.
332
- Chantal Ykman-Couvreur:
Exploration framework for Run-time Resource Management of embedded multi-core platforms.
333-340
- Michael A. Hicks, Michiel W. van Tol, Chris R. Jesshope:
Towards scalable I/O on a many-core architecture.
341-348
- Gabriel Falcão Paiva Fernandes, Leonel Sousa, Vítor Manuel Mendes da Silva:
Embedded multicore architectures for LDPC decoding.
349-356
- Diana Göhringer, Michael Hübner, Laure Hugot-Derville, Jürgen Becker:
Message Passing Interface support for the runtime adaptive multi-processor system-on-chip RAMPSoC.
357-364
- Fabio Arlati, Francesco Bruschi, Donatella Sciuto:
Designing and validating access policies to reconfigurable resources in Multiprocessor Systems on chip.
365-371
- Dmitry Nadezhkin, Todor Stefanov:
Identifying communication models in Process Networks derived from Weakly Dynamic Programs.
372-379
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