• 
  Adel Dokhanchi, Ali Jahanian, Esfandiar Mehrshahi, Mohammad Taghi Teimoori: Feasibility Study of Using the RF Interconnects in Large FPGAs to Improve Routing Tracks Usage. 1-6
• 
  Avinash Lakshminarayana, Sumit Ahuja, Sandeep K. Shukla: High Level Power Estimation Models for FPGAs. 7-12
• 
  Matthias Kühnle, Alisson Vasconcelos De Brito, Christoph Roth, Konstantinos Dagas, Jürgen Becker: The Study of a Dynamic Reconfiguration Manager for Systems-on-Chip. 13-18

Three-Dimensional ICs

• 
  Chaochao Feng, Minxuan Zhang, Jinwen Li, Jiang Jiang, Zhonghai Lu, Axel Jantsch: A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip. 19-24
• 
  Florian Darve, Abbas Sheibanyrad, Pascal Vivet, Frédéric Pétrot: Physical Implementation of an Asynchronous 3D-NoC Router Using Serial Vertical Links. 25-30
• 
  Surajit Kumar Roy, Chandan Giri, Sourav Ghosh, Hafizur Rahaman: Optimizing Test Wrapper for Embedded Cores Using TSV Based 3D SOCs. 31-36

Nanoelectronics

• 
  Ramesh Vaddi, Sudeb Dasgupta, R. P. Agarwal: Effect of Gate-S/D Underlap, Asymmetric and Independent Gate Features in the Minimization of Short Channel Effects in Nanoscale DGMOSFET. 37-42
• 
  Ganesh C. Patil, S. Qureshi: Asymmetric Drain Underlap Schottky Barrier SOI MOSFET for Low-Power High Performance Nanoscale CMOS Circuits. 43-48
• 
  Shashank Parashar, Chaudhry Indra Kumar, Manisha Pattanaik: An Efficient Design Technique for High Performance Dynamic Feedthrough Logic with Enhanced Noise Tolerance. 49-53

Network-on-Chips

• 
  Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli: A DRAM Centric NoC Architecture and Topology Design Approach. 54-59
• 
  M. Pawan Kumar, Anish S. Kumar, Srinivasan Murali, Luca Benini, Kamakoti Veezhinathan: A Method for Integrating Network-on-Chip Topologies with 3D ICs. 60-65
• 
  Weichen Liu, Jiang Xu, Xiaowen Wu, Yaoyao Ye, Xuan Wang, Wei Zhang, Mahdi Nikdast, Zhehui Wang: A NoC Traffic Suite Based on Real Applications. 66-71

Mixed Signal Design

• 
  Menka Sukhwani, Vinay Bhaskar Chandratre, Megha Thomas, C. K. Pithawa, Vangmayee Sharda: 500 MHz Delay Locked Loop Based 128-bin, 256 ns Deep Analog Memory ASIC "Anusmriti". 72-77
• 
  S. R. Sant, S. S. Waikar, Marshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma: A 16-Gbps 9mW Transmitter with FFE in 90nm CMOS Technology for Off-Chip Communication. 78-83
• 
  Arnab Khawas, Amitava Banerjee, Siddhartha Mukhopadhyay: A Response Surface Method for Design Space Exploration and Optimization of Analog Circuits. 84-89

Placement

• 
  B. N. B. Ray, Shankar Balachandran: A New Wirelength Model for Analytical Placement. 90-95
• 
  Yiqiang Sheng, Atsushi Takahashi, Shuichi Ueno: Relay-Race Algorithm: A Novel Heuristic Approach to VLSI/PCB Placement. 96-101
• 
  Evriklis Kounalakis, Christos P. Sotiriou, Vassilis Zebilis: Statistical Timing-Based Post-Placement Leakage Recovery. 102-107

VLSI Circuits

• 
  Arnab K. Biswas, A. Bulusu, S. Dasgupta: A Proposed Output Buffer at 90 nm Technology with Minimum Signal Switching Noise at 83.3MHz. 108-113
• 
  Manas Kumar Hati, Tarun Kanti Bhattacharyya: Design of a Low Power, High Speed Complementary Input Folded Regulated Cascode OTA for a Parallel Pipeline ADC. 114-119

Reversible Logic

• 
  Robert Wille, Hongyan Zhang, Rolf Drechsler: ATPG for Reversible Circuits Using Simulation, Boolean Satisfiability, and Pseudo Boolean Optimization. 120-125
• 
  Matthew Morrison, Nagarajan Ranganathan: Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures. 126-131

Clock Network Design

• 
  Naveen Kumar Kancharapu, Marshnil Vipin Dave, Veerraju Masimukkula, Maryam Shojaei Baghini, Dinesh Kumar Sharma: A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology. 132-137
• 
  Zohre Mohammadi-Arfa, Ali Jahanian: A Hybrid RF/Metal Clock Routing Algorithm to Improve Clock Delay and Routing Congestion. 138-143
• 
  Ya-Shih Huang, Yang-Hsiang Liu, Juinn-Dar Huang: Layer-Aware Design Partitioning for Vertical Interconnect Minimization. 144-149

Verification

• 
  Ansuman Banerjee: Requirement Evolution Management: A Systematic Approach. 150-155
• 
  Chandan Karfa, Kunal Banerjee, Dipankar Sarkar, Chitta Mandal: Equivalence Checking of Array-Intensive Programs. 156-161
• 
  Vinitha Arakkonam Palaniveloo, Arcot Sowmya: Application of Formal Methods for System-Level Verification of Network on Chip. 162-169

Low Power 1

• 
  Jing Cao, Albert Nymeyer: A Markov Performance Model for Buffered Protocol Design. 170-175
• 
  Charvi Dhoot, Vincent John Mooney, Lap Pui Chau, Shubhajit Roy Chowdhury: Low Power Motion Estimation with Probabilistic Computing. 176-181
• 
  Aman Gupta, Satyam Mandavalli, Vincent John Mooney, Keck Voon Ling, Arindam Basu, Henry Johan, Budianto Tandianus: Low Power Probabilistic Floating Point Multiplier Design. 182-187

Physical Design

• 
  Ayan Datta, Charudhattan Nagarajan, Susmita Sur-Kolay: TSV-aware Scan Chain Reordering for 3D IC. 188-193
• 
  Michael Buttrick, Sandip Kundu: Mitigating Partitioning, Routing, and Yield Concerns in 3D ICs by Multiplexing TSVs. 194-199
• 
  Nishant Dhumane, Sudheendra K. Srivathsa, Sandip Kundu: Lithography Constrained Placement and Post-Placement Layout Optimization for Manufacturability. 200-205

Interconnec

• 
  Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli: A Simulation Based Buffer Sizing Algorithm for Network on Chips. 206-211
• 
  Shuzhe Zhou, Hailong Yao, Qiang Zhou, Yici Cai: Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment. 212-217
• 
  Ting-Feng Chang, Tsang-Chi Kan, Shih-Hsien Yang, Shanq-Jang Ruan: Enhanced Redundant via Insertion with Multi-via Mechanisms. 218-223

Security

• 
  Raghavan Kumar, Vinay C. Patil, Sandip Kundu: Design of Unique and Reliable Physically Unclonable Functions Based on Current Starved Inverter Chain. 224-229
• 
  Han-Wei Chen, Suresh Srinivasan, Yuan Xie, Vijaykrishnan Narayanan: Impact of Circuit Degradation on FPGA Design Security. 230-235
• 
  Karthik Swaminathan, Ravindhiran Mukundrajan, Niranjan Soundararajan, Vijaykrishnan Narayanan: Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM. 236-241

Emerging Trends

• 
  Behnam Ghavami, Mohsen Raji, Hossein Pedram: Metallic-CNT and Non-uniform CNTs Tolerant Design of CNFET-based Circuits Using Independent N2-Transistor Structures. 242-247
• 
  Vikram B. Suresh, Priyamvada Vijayakumar, Sandip Kundu: On Screening Reliability Using Lithographic Process Corner Information Gleaned from Tester Measurements. 248-253
• 
  Yaoyao Ye, Jiang Xu, Xiaowen Wu, Wei Zhang, Xuan Wang, Mahdi Nikdast, Zhehui Wang, Weichen Liu: Modeling and Analysis of Thermal Effects in Optical Networks-on-Chip. 254-259

System Level Synthesis

• 
  Weichen Liu, Jiang Xu, Xuan Wang, Yu Wang, Wei Zhang, Yaoyao Ye, Xiaowen Wu, Mahdi Nikdast, Zhehui Wang: A Hardware-Software Collaborated Method for Soft-Error Tolerant MPSoC. 260-265
• 
  Li Tang, Shuai Wang, Jie S. Hu, Xiaobo Sharon Hu: Characterizing the L1 Data Cache's Vulnerability to Transient Errors in Chip-Multiprocessors. 266-271
• 
  Yaohua Wang, Shuming Chen, Jianghua Wan, Kai Zhang, Shenggang Chen: AIFSP: An Adaptive Instruction Flow Stream Processor. 272-277

Low Power 2

• 
  Sharad Sinha, Udit Dhawan, Siew Kei Lam, Thambipillai Srikanthan: A Novel Binding Algorithm to Reduce Critical Path Delay During High Level Synthesis. 278-283
• 
  P. Rajshekar, M. Malathi: Power Efficient Multiplexer Using DLDFF Synchronous Counter. 284-289
• 
  D. S. Harish Ram, M. C. Bhuvaneswari, S. M. Logesh: A Novel Evolutionary Technique for Multi-objective Power, Area and Delay Optimization in High Level Synthesis of Datapaths. 290-295

High Level Synthesis

• 
  Deepak Dasalukunte, Fredrik Rusek, Viktor Öwall: Improved Memory Architecture for Multicarrier Faster-than-Nyquist Iterative Decoder. 296-300
• 
  Babak Hidaji, Salar Alipour, Kasyab P. Subramaniyan, Per Larsson-Edefors: Application-Specific Energy Optimization of General-Purpose Datapath Interconnect. 301-306
• 
  Varun Vasudevan, Vinay Sheshadri, Sivarama Krishnan R., K. S. Vasundara Patel: Design and Complexity Analysis of Reed Solomon Code Algorithm for Advanced RAID System in Quaternary Domain. 307-312

Poster Session MP1

• 
  Chandan Karfa, Chitta Mandal, Dipankar Sarkar: Verification of Register Transfer Level Low Power Transformations. 313-314
• 
  Gracieli Posser, Guilherme Flach, Gustavo Wilke, Ricardo Reis: Gate Sizing Minimizing Delay and Area. 315-316
• 
  Pranab Roy, Rajesh Mandal, Hafizur Rahaman, Parthasarathi Dasgupta: A Group-Preferential Parallel-Routing Algorithm for Cross-Referencing Digital Microfluidic Biochips. 317-318
• 
  Seetal Potluri, Nitin Chandrachoodan, V. Kamakoti: Post-Synthesis Circuit Techniques for Runtime Leakage Reduction. 319-320
• 
  Lilia Zaourar, Yann Kieffer, Chouki Aktouf: A Global Optimization for Scan Chain Insertion at the RT-level. 321-322
• 
  Rashmi K. Lomte, P. C. Bhaskar: High Speed Convolution and Deconvolution Using Urdhva Triyagbhyam. 323-324

Poster Session MP2

• 
  Arnab Khawas, Siddhartha Mukhopadhyay: A Design of Experiment Based Approach to Variance Optimal Design of CMOS OpAmp. 325-326
• 
  Harshit Agnihotri, Abhishek Ranjan, Pramod Kumar Tiwari, Satyabrata Jit: An Analytical Drain Current Model for Short-Channel Triple-Material Double-Gate MOSFETs. 327-328
• 
  Garima Kapur, Kapil Bhola, C. M. Markan: Design to Introduce On-chip Fine Tunability in Analog Active Inductor. 329-330
• 
  Fataneh Jafari, Mahdi Mosaffa, Siamak Mohammadi: On the Potentials of FinFETs for Asynchronous Circuit Design. 331-332
• 
  Prafulla Galphade, Rasika Dhavse: Modeling Study of Impact of Surface Roughness on Flicker Noise in MOSFET. 333-334

Poster Session WP1

• 
  Pradip Kumar Sahu, Putta Venkatesh, Sunilraju Gollapalli, Santanu Chattopadhyay: Application Mapping onto Mesh Structured Network-on-Chip Using Particle Swarm Optimization. 335-336
• 
  Samarth Kaushik, Amit Kumar Singh, Thambipillai Srikanthan: Preprocessing-Based Run-Time Mapping of Applications on NoC-based MPSoCs. 337-338
• 
  Amit Kumar Singh, Akash Kumar, Thambipillai Srikanthan: A Design Space Exploration Methodology for Application Specific MPSoC Design. 339-340
• 
  Soumya J., Putta Venkatesh, Santanu Chattopadhyay: Flexible Router Placement with Link Length and Port Constraints for Application-Specific Network-on-Chip Synthesis. 341-342
• 
  Andreas G. Savva, Theocharis Theocharides, Vassos Soteriou: Intelligent On/Off Link Management for On-chip Networks. 343-344

Poster Session WP2

• 
  Mallikarjuna Rao Nimmagadda, Ajit Pal: Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design. 345-346
• 
  B. Sandeep Kumar, Vikram Pudi, K. Sridharan: Efficient VLSI Architectures for the Hadamard Transform Based on Offset-Binary Coding and ROM Decomposition. 347-348
• 
  Chetan Kumar V., Sai Phaneendra P., Syed Ershad Ahmed, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas: A Prefix Based Reconfigurable Adder. 349-350
• 
  Amit Pande, Joseph Zambreno, Prasant Mohapatra: Architectures for Simultaneous Coding and Encryption Using Chaotic Maps. 351-352
• 
  Anita Arvind Deshmukh, Raghevendra Deshmukh, Rajendra Patrikar: Low Power Asynchronous Sigma-Delta Modulator Using Hysteresis Level Control. 353-354

PhD Forum

• 
  Amir-Mohammad Rahmani, Khalid Latif, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Power-Efficient Inter-Layer Communication Architectures for 3D NoC. 355-356
• 
  Santanu Kundu, Santanu Chattopadhyay: Design and Evaluation of Mesh-of-Tree Based Network-on-Chip for Two- and Three-Dimensional Integrated Circuits. 357-358
• 
  Deepak Dasalukunte, Fredrik Rusek, John B. Anderson, Viktor Öwall: Design and Implementation of Iterative Decoder for Faster-than-Nyquist Signaling Multicarrier Systems. 359-360
• 
  Alpana Agarwal, Chandra Shekhar: Synthesis of Analog IC Building Blocks. 361-362
• 
  Santosh Ghosh: Design and Analysis of Pairing Based Cryptographic Hardware for Prime Fields. 363-364
• 
  G. Indumathi, K. V. Ramakrishnan: Study and Analysis of Power Optimization Techniques for Embedded Systems. 365-366
• 
  David Fuschelberger, Ioannis Pyrounakis, Tasos Dagiuklas, Nikolaos S. Voros, Carlos Ribeiro: Next Generation Smart Home Systems Using Hardware Acceleration Techniques. 367-368
• 
  Chia-I Chen, Juinn-Dar Huang: Architectural Synthesis Frameworks on Distributed Register-File Microarchitecture Family. 369-370
• 
  Kameswar Rao Vaddina, Amir-Mohammad Rahmani, Khalid Latif, Pasi Liljeberg, Juha Plosila: Thermal Analysis of Advanced 3D Stacked Systems. 371-372

last updated on Mon May 20 02:23:04 2013 by the dblp team
data released under the ODC-BY 1.0 license
see also our legal information page