ISVLSI 2010: Lixouri Kefalonia, Greece

• Panagiotis Tsarchopoulos:
  European ICT Research: 2011-2012 Outlook for Components and Systems. 1-2
  
• Krishnendu Chakrabarty:
  Digital Microfluidic Biochips: A Vision for Functional Diversity and More Than Moore. 3-4
  
• Marcello Coppola:
  Small Worlds: The Dynamics of NoCs in Tomorrow SoC Architecture. 5
  
• Apostolos Dollas:
  Reconfigurable Architectures for Bioinformatics Applications. 6-7
  
• Christian Gamrat:
  Challenges and Perspectives of Computer Architecture at the Nano Scale. 8-10
  
• Evangelos Vassalos, Dimitris Bakalis, Haridimos T. Vergos:
  SUT-RNS Forward and Reverse Converters. 11-16
  
• Jianchao Lu, Baris Taskin:
  Clock Tree Synthesis with XOR Gates for Polarity Assignment. 17-22
  
• Christian Pilato, Fabrizio Ferrandi, Davide Pandini:
  A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells. 23-28
  
• Gopal Paul, Rohit Reddy, Chittaranjan A. Mandal, Bhargab B. Bhattacharya:
  A BDD-Based Design of an Area-Power Efficient Asynchronous Adder. 29-34
  
• Nikolaos Kavvadias, Konstantinos Masselos:
  Efficient Hardware Looping Units for FPGAs. 35-40
  
• Efthymia Arvaniti, Ilias Mavridis, Athanasios Kakarountas:
  Exploration of 2D Cellular Automata as Binary Sequence Generators. 41-45
  
• Tayyeb Mahmood, Soontae Kim:
  Fine-Grained Fault Tolerance for Process Variation-Aware Caches. 46-51
  
• Prakash Srinivasan, Ronan Farrell:
  Hierarchical DFT with Combinational Scan Compression, Partition Chain and RPCT. 52-57
  
• Farid Lahrach, Abderrahim Doumar, Eric Châtelet, Abderrazek Abdaoui:
  Master-Slave TMR Inspired Technique for Fault Tolerance of SRAM-Based FPGA. 58-62
  
• Vasileios Tenentes, Xrysovalantis Kavousianos:
  Self-Freeze Linear Decompressors for Low Power Testing. 63-68
  
• Felipe Pinto, Lucas Cavalheiro, Marcelo de Oliveira Johann, Ricardo Reis:
  Logical Core Algorithm: Improving Global Placement. 69-73
  
• Romuald Girardey, Michael Hübner, Jürgen Becker:
  Safety Aware Place and Route for On-Chip Redundancy in Safety Critical Applications. 74-79
  
• Ming Liu, Zhonghai Lu, Wolfgang Kuehn, Axel Jantsch:
  Inter-process Communication Using Pipes in FPGA-Based Adaptive Computing. 80-85
  
• Ronaldo Husemann, Mariano Majolo, Altamiro Amadeu Susin, Valter Roesler, José Valdeni de Lima:
  Highly Efficient Transforms Module Solution for a H.264/SVC Encoder. 86-91
  
• Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
  Input-Output Selection Based Router for Networks-on-Chip. 92-97
  
• Michael F. Dossis:
  Automatic Generation of Massively Parallel Hardware from Control-Intensive Sequential Programs. 98-103
  
• Sotirios Xydis, Christos Skouroumounis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos:
  Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching. 104-109
  
• David Cuesta, José L. Ayala, José Ignacio Hidalgo, David Atienza, Andrea Acquaviva, Enrico Macii:
  Adaptive Task Migration Policies for Thermal Control in MPSoCs. 110-115
  
• Vikram Sampath Kumar, Kevin M. Irick, Ahmed Al-Maashri, Narayanan Vijaykrishnan:
  A Scalable Bandwidth Aware Architecture for Connected Component Labeling. 116-121
  
• David Stevens, Vassilios Chouliaras:
  LE1: A Parameterizable VLIW Chip-Multiprocessor with Hardware PThreads Support. 122-126
  
• Daniel P. Volpato, Alexandre K. I. Mendonça, Luiz C. V. dos Santos, José Luís Güntzel:
  A Post-compiling Approach that Exploits Code Granularity in Scratchpads to Improve Energy Efficiency. 127-132
  
• Iasonas Filippopoulos, Iraklis Anagnostopoulos, Alexandros Bartzas, Dimitrios Soudris, George Economakos:
  Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures. 133-138
  
• Nicolas Sklavos, Paris Kitsos:
  BLAKE HASH Function Family on FPGA: From the Fastest to the Smallest. 139-142
  
• Keanhong Boey, Yingxi Lu, Máire O'Neill, Roger Woods:
  Differential Power Analysis of CAST-128. 143-148
  
• Liang Lu, Weiqiang Liu, Máire O'Neill, Earl E. Swartzlander Jr.:
  QCA Systolic Matrix Multiplier. 149-154
  
• Apostolos P. Fournaris:
  Hardware Module Design for Ensuring Trust. 155-160
  
• Prasenjit Biswas, Pramod P. Udupa, Rajdeep Mondal, Keshavan Varadarajan, Mythri Alle, S. K. Nandy, Ranjani Narayan:
  Accelerating Numerical Linear Algebra Kernels on a Scalable Run Time Reconfigurable Platform. 161-166
  
• Mohammad Hosseinabady, Jose Luis Nunez-Yanez, Antonio Marcello Coppola:
  Task Dispersal Measurement in Dynamic Reconfigurable NoCs. 167-172
  
• Behnam Ghavami, Alireza Tajary, Mohsen Raji, Hossein Pedram:
  Defect and Variation Issues on Design Mapping of Reconfigurable Nanoscale Crossbars. 173-178
  
• Zulhakimi Razak, Ahmet T. Erdogan, Tughrul Arslan:
  ASIC Design of an Adaptive Control Unit for Reconfigurable Analog-to-Digital Converters. 179-184
  
• Salwa Mostafa, Wenchao Qu, Syed Kamrul Islam, Mohamed Mahfouz:
  A Calibration Circuit for Reconfigurable Smart ADC for Biomedical Signal Processing. 185-189
  
• Michael Hübner, Joachim Meyer, Oliver Sander, Lars Braun, Jürgen Becker, Juanjo Noguera, Rodney Stewart:
  Fast Sequential FPGA Startup Based on Partial and Dynamic Reconfiguration. 190-194
  
• Mehrdad Khatir, Alireza Ejlali:
  A Body Biasing Method for Charge Recovery Circuits: Improving the Energy Efficiency and DPA-Immunity. 195-200
  
• Themistoklis Haniotakis, Zaher Owda, Yiorgos Tsiatouhas:
  Memory-Less Pipeline Dynamic Circuit Design Technique. 201-205
  
• V. Suresh Babu, P. S. Haseena, M. R. Baiju:
  A Floating Gate MOSFET Based Current Reference with Subtraction Technique. 206-209
  
• Samuel Leshner, Krzysztof S. Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, Sarma B. K. Vrudhula:
  A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS. 210-215
  
• Ali M. Farhangi, Asim J. Al-Khalili, Dhamin Al-Khalili:
  Pattern-Driven Clock Tree Routing with Via Minimization. 216-221
  
• Mohammad Rafiqul Haider, Ashraf B. Islam, Syed Kamrul Islam:
  Ultra-Low-Power Sensor Signal Monitoring and Impulse Radio Architecture for Biomedical Applications. 222-227
  
• Ankit More, Baris Taskin:
  Simulation Based Feasibility Study of Wireless RF Interconnects for 3D ICs. 228-231
  
• Alexios Spyronasios, Michael G. Dimopoulos, Nikolaos P. Papadopoulos, Alkis A. Hatzopoulos:
  Testing Parametric and Catastrophic Faults in Mixed-Signal Integrated Circuits Using Wavelets. 232-237
  
• Yiannis Moisiadis, Yiorgos Tsiatouhas:
  A Receiver Circuit for Low-Swing Interconnect Schemes. 238-241
  
• Nikos Petrellis, Michael K. Birbas, John C. Kikidis, Alexios N. Birbas:
  An 8-Bit Voltage Mode Analog to Digital Converter Based on Integer Division. 242-246
  
• Kapil K. Rajput, Anil K. Saini, Subash C. Bose:
  DC Offset Modeling and Noise Minimization for Differential Amplifier in Subthreshold Operation. 247-252
  
• Zach Cashero, Allen Chen, Ryan Hoppal, Tom Chen:
  Fast Evaluation of Analog Circuits Using Linear Programming. 253-258
  
• Stylianos Siskos:
  FGMOS Based Built-In Current Sensor for Low Supply Voltage Analog and Mixed-Signal Circuits Testing. 259-264
  
• Kai Zhu, Mohammad Rafiqul Haider, Song Yuan, Syed Kamrul Islam:
  A Sub-1μA Low-Power FSK Modulator for Biomedical Sensor Circuits. 265-268
  
• E. Vilella, Ángel Diéguez:
  Design of a Bandgap Reference Circuit with Trimming for Operation at Multiple Voltages and Tolerant to Radiation in 90nm CMOS Technology. 269-272
  
• Thomas Tsiolakis, George Alexiou, Nikolaos Konofaos:
  Low Power Single Electron Or/Nor Gate Operating at 10GHz. 273-276
  
• Zhou Hailiang, Zhang Minxuan, Fang Liang, Hao Yue:
  Performance Optimization of Conventional MOS-Like Carbon Nanotube-FETs Based on Dual-Gate-Material. 277-281
  
• Guilherme Flach, Gustavo Wilke, Marcelo O. Johann, Ricardo Reis:
  A Mesh-Buffer Displacement Optimization Strategy. 282-287
  
• Srinidhi Kestur, John D. Davis, Oliver Williams:
  BLAS Comparison on FPGA, CPU and GPU. 288-293
  
• Vipparla Chandrakanth, Ramachandra Kuloor:
  Novel Architecture for Highly Hardware Efficient Implementation of Real Time Matrix Inversion Using Gauss Jordan Technique. 294-298
  
• Mahtab Niknahad, Michael Hübner, Jürgen Becker:
  Reliability Analysis and Improvement in Nano Scale Design. 299-303
  
• Farshad Firouzi, Mostafa E. Salehi, Fan Wang, Sied Mehdi Fakhraie, Saeed Safari:
  Reliability-Aware Dynamic Voltage and Frequency Scaling. 304-309
  
• Shuai Wang, Jie S. Hu, Sotirios G. Ziavras:
  TRB: Tag Replication Buffer for Enhancing the Reliability of the Cache Tag Array. 310-315
  
• Shubo Qi, Jinwen Li, Zuocheng Xing, Xiaomin Jia, Minxuan Zhang:
  A Delay Model of Two-Cycle NoC Router in 2D-Mesh Network. 316-320
  
• Hsin-Chou Chi, Yu-Hong Jhang, Wen-Shu Chen:
  Tree-Based Routing for Faulty On-Chip Networks with Mesh Topology. 321-326
  
• Mo Kwai Hung, Yaoyao Ye, Xiaowen Wu, Wei Zhang, Weichen Liu, Jiang Xu:
  A Hierarchical Hybrid Optical-Electronic Network-on-Chip. 327-332
  
• Mohammad Fattah, Abdurrahman Manian, Abbas Rahimi, Siamak Mohammadi:
  A High Throughput Low Power FIFO Used for GALS NoC Buffers. 333-338
  
• Elena Kakoulli, Vassos Soteriou, Theocharis Theocharides:
  An Artificial Neural Network-Based Hotspot Prediction Mechanism for NoCs. 339-344
  
• Camille Jalier, Didier Lattard, Gilles Sassatelli, Pascal Benoit, Lionel Torres:
  A Homogeneous MPSoC with Dynamic Task Mapping for Software Defined Radio. 345-350
  
• Ulhas Deshmukh, Vineet Sahula:
  Stochastic Automata Network Based Approach for Performance Evaluation of Network-on-Chip Communication Architecture. 351-356
  
• Naoya Onizawa, Tomoyoshi Funazaki, Atsushi Matsumoto, Takahiro Hanyu:
  Accurate Asynchronous Network-on-Chip Simulation Based on a Delay-Aware Model. 357-362
  
• Pavel Ghosh, Arvind Ravi, Arunabha Sen:
  An Analytical Framework with Bounded Deflection Adaptive Routing for Networks-on-Chip. 363-368
  
• Shijun Lin, Jianghong Shi, Huihuang Chen:
  Hybrid QoS Method for Networks-on-Chip. 369-374
  
• Theodoros Lioris, Grigoris Dimitroulakos, Kostas Masselos:
  XMSIM: EXtensible Memory SIMulator for Early Memory Hierarchy Evaluation. 375-380
  
• R. K. Sharma, Aditi Sood:
  Modeling and Simulation of Multi-operation Microcode-Based Built-In Self Test for Memory Fault Detection and Repair. 381-386
  
• Alexis Alexandropoulos, Efthimios Davrazos, Fotis Plessas, Michael K. Birbas:
  A Novel 1.8 V, 1066 Mbps, DDR2, DFI-Compatible, Memory Interface. 387-392
  
• Taniya Siddiqua, Sudhanva Gurumurthi:
  Recovery Boosting: A Technique to Enhance NBTI Recovery in SRAM Arrays. 393-398
  
• Nicholas Axelos, Kiamal Z. Pekmestzi, Nikolaos Moschopoulos:
  A New Low-Power Soft-Error Tolerant SRAM Cell. 399-404
  
• Anastasios Karagounis, Basilis Kotsos, Nikolaos Assimakis, Eyrikleia Petropoulou, Athanasios Polyzos:
  The Impact of Process Faults on Specific Parameters of a 1.9GHz CMOS Mixer. 405-409
  
• Costas Argyrides, Nikolaos Mavrogiannakis, Dhiraj K. Pradhan:
  Improved Yield in Nanotechnology Circuits Using Non-square Meshes. 410-415
  
• Erick Amador, Raymond Knopp, Vincent Rezard, Renaud Pacalet:
  Dynamic Power Management on LDPC Decoders. 416-421
  
• Imen Mansouri, Camille Jalier, Fabien Clermidy, Pascal Benoit, Lionel Torres:
  Implementation Analysis of a Dynamic Energy Management Approach Inspired by Game-Theory. 422-427
  
• Chandan Karfa, Dipankar Sarkar, Chittaranjan A. Mandal:
  Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques. 428-433
  
• Mahesh Kumar Adimulam, Sreehari Veeramachaneni, N. Moorthy Muthukrishnan, M. B. Srinivas:
  A Novel, Variable Resolution Flash ADC with Sub Flash Architecture. 434-435
  
• Mark G. Arnold, Panagiotis D. Vouzis, Jung H. Cho:
  Bitstream Efficiency of Field Programmable One-Hot Arrays. 436-441
  
• Haridimos T. Vergos:
  A Family of Area-Time Efficient Modulo 2n+1 Adders. 442-443
  
• Kostas Siozios, Iraklis Anagnostopoulos, Dimitrios Soudris:
  A High-Level Mapping Algorithm Targeting 3D NoC Architectures with Multiple Vdd. 444-445
  
• Kostas Siozios, Dimitrios Soudris, Dionisios N. Pnevmatikatos:
  Towards Supporting Fault-Tolerance in FPGAs. 446-447
  
• Usha Sandeep Mehta, Niranjan M. Devashrayee, Kankar S. Dasgupta:
  Combining Unspecified Test Data Bit Filling Methods and Run Length Based Codes to Estimate Compression, Power and Area Overhead. 448-449
  
• Xiaofang Wang:
  A Novel On-Chip Interconnection Topology for Mesh-Connected Processor Arrays. 450-451
  
• Amir-Mohammad Rahmani, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
  BBVC-3D-NoC: An Efficient 3D NoC Architecture Using Bidirectional Bisynchronous Vertical Channels. 452-453
  
• Alen Bardizbanyan, Kasyab P. Subramaniyan, Per Larsson-Edefors:
  Generation and Exploration of Layouts for Area-Efficient Barrel Shifters. 454-455
  
• Amir Sabbagh Molahosseini, Keivan Navi:
  A Reverse Converter for the Enhanced Moduli Set {2n-1, 2n+1, 22n, 22n+1-1} Using CRT and MRC. 456-457
  
• Marco Lanuzza, Raffaele De Rose, Fabio Frustaci, Stefania Perri, Pasquale Corsonello:
  Impact of Process Variations on Flip-Flops Energy and Timing Characteristics. 458-459
  
• Anestis Bechtsoudis, Nicolas Sklavos:
  Side Channel Attacks Cryptanalysis against Block Ciphers Based on FPGA Devices. 460-461
  
• Xiaowen Chen, Zhonghai Lu, Axel Jantsch, Shuming Chen, Jianzhuang Lu, Hucheng Wu:
  Supporting Efficient Synchronization in Multi-core NoCs Using Dynamic Buffer Allocation Technique. 462-463
  
• Ludovic A. Krundel, David J. Mulvaney, Vassilios A. Chouliaras:
  Autonomous Design in VLSI: An In-House Universal Cellular Neural Platform. 464-466
  
• Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
  High-Performance TSV Architecture for 3-D ICs. 467-468
  
• Romuald Girardey, Michael Hübner, Jürgen Becker:
  Mixed-Signal Diverse Redundant System for Safety Critical Applications in FPGA. 469-470
  
• Vinayak Honkote:
  Design Automation and Analysis of Resonant Rotary Clocking Technology. 471-472
  
• Georgia Kalogeridou, Nikolaos S. Voros, Konstantinos Masselos:
  System Level Design of Complex Hardware Applications Using ImpulseC. 473-474
  
• Lars Braun, Jürgen Becker:
  Two-Dimensional Dynamic Multigrained Reconfigurable Hardware. 475-476
  
• Diana Göhringer, Jürgen Becker:
  FPGA-Based Runtime Adaptive Multiprocessor Approach for Embedded High Performance Computing Applications. 477-478
  
• Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Hannu Tenhunen:
  Performance Analysis of 3D NoCs Partitioning Methods. 479-480
  
• Ludovic A. Krundel, David J. Mulvaney, Vassilios A. Chouliaras:
  Autonomous Design in VLSI: Growing and Learning on Silicon. 481-485
  
• Sotirios Xydis, Kiamal Z. Pekmestzi, Dimitrios Soudris, George Economakos:
  High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures. 486-487
  
• Cristina Silvano, William Fornaciari, Gianluca Palermo, Vittorio Zaccaria, Fabrizio Castro, Marcos Martínez, Sara Bocchio, Roberto Zafalon, Prabhat Avasare, Geert Vanmeerbeeck, Chantal Ykman-Couvreur, Maryse Wouters, Carlos Kavka, Luka Onesti, Alessandro Turco, Umberto Bondi, Giovanni Mariani, Hector Posadas, Eugenio Villar, Chris Wu, Dongrui Fan, Zhang Hao, Shibin Tang:
  MULTICUBE: Multi-objective Design Space Exploration of Multi-core Architectures. 488-493
  
• Cristina Silvano, William Fornaciari, Stefano Crespi-Reghizzi, Giovanni Agosta, Gianluca Palermo, Vittorio Zaccaria, Patrick Bellasi, Fabrizio Castro, Simone Corbetta, Andrea Di Biagio, Ettore Speziale, Michele Tartara, David Siorpaes, Heiko Hübert, Benno Stabernack, Jens Brandenburg, Martin Palkovic, Praveen Raghavan, Chantal Ykman-Couvreur, Alexandros Bartzas, Sotirios Xydis, Dimitrios Soudris, Torsten Kempf, Gerd Ascheid, Rainer Leupers, Heinrich Meyr, Junaid Ansari, Petri Mähönen, Bart Vanthournout:
  2PARMA: Parallel Paradigms and Run-Time Management Techniques for Many-Core Architectures. 494-499
  
• Paul Brelet, Arnaud Grasset, Philippe Bonnot, Frank Ieromnimon, Dimitrios Kritharidis, Nikolaos S. Voros:
  System Level Design for Embedded Reconfigurable Systems Using MORPHEUS Platform. 500-505
  
• Wolfgang Müller, Da He, Fabian Mischkalla, Arthur Wegele, Paul Whiston, Pablo Peñil, Eugenio Villar, Nikolaos Mitas, Dimitrios Kritharidis, Florent Azcarate, Manuel Carballeda:
  The SATURN Approach to SysML-Based HW/SW Codesign. 506-511
  
• Christos Baloukas, Lazaros Papadopoulos, Dimitrios Soudris, Sander Stuijk, Olivera Jovanovic, Florian Schmoll, Daniel Cordes, Robert Pyka, Arindam Mallik, Stylianos Mamagkakis, François Capman, Séverin Collet, Nikolaos Mitas, Dimitrios Kritharidis:
  Mapping Embedded Applications on MPSoCs: The MNEMEE Approach. 512-517
  
• Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin:
  Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach. 518-523
  

Last update Fri May 25 08:24:26 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page