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2010 – 2019
- 2014
[c16]Hsin-Chou Chi, Han-Sheng Liu, Hsi-Che Tseng:
A high-performance VLSI architecture for variable block size motion estimation. GCCE 2014: 123-124- 2013
- [c15]Hsin-Chou Chi, Hsi-Che Tseng, Chia-Wei Jeng:
Reconfigurable VLSI digital filters for tolerating multiple timing errors. GCCE 2013: 149-150 - 2012
- [c14]Hsin-Chou Chi, Jr-Fen Ferng, Yu-Chen Hsieh:
Area Utilization Based Mapping for Network-on-chip Architectures with Over-sized IP Cores. HPCC-ICESS 2012: 1520-1525 - 2011
- [c13]Hsin-Chou Chi, Hsi-Che Tseng, Kun-Lin Tsai:
Design of timing-error-resilient systolic arrays for matrix multiplication. ISOCC 2011: 219-222 - [c12]Hsin-Chou Chi, Hsi-Che Tseng, Chih-Ling Yang:
Efficient diagnosable design of the IEEE P1500 architecture for SoC testing. NESEA 2011: 1-7 - 2010
- [c11]Hsin-Chou Chi, Yu-Hong Jhang, Wen-Shu Chen:
Tree-Based Routing for Faulty On-Chip Networks with Mesh Topology. ISVLSI 2010: 321-326 - [c10]Hsin-Chou Chi, Tat-Seng Chang, Chia-Ming Wu:
Design of a Reconfigurable Pipelined Switch for Faulty On-Chip Networks. SIES 2010: 51-56
2000 – 2009
- 2009
- [c9]Hsin-Chou Chi, Hsi-Che Tseng, Chih-Ling Yang:
Efficient diagnosis of scan chains with single stuck-at faults. CISS 2009: 473-476 - 2008
- [c8]Hsin-Chou Chi, Chia-Ming Wu, Jun-Hui Lee:
Integrated Mapping and Scheduling for Circuit-Switched Network-on-Chip Architectures. DELTA 2008: 415-420 - 2006
- [c7]Hsin-Chou Chi, Chia-Ming Wu, Sung-Tze Wu:
A Switch Supporting Circuit and Packet Switching for On-Chip Networks. DDECS 2006: 226-227 - [c6]Hsin-Chou Chi, Chia-Ming Wu:
An Efficient Scheduler for Circuit-Switched Network-on-Chip Architectures. VLSI-SoC 2006: 68-73 - 2005
- [c5]Hsin-Chou Chi, Chia-Ming Wu:
Efficient Switches for Network-on-Chip Based Embedded Systems. EUC 2005: 67-76 - 2003
- [c4]Hsin-Chou Chi, Wen-Jen Wu:
Routing Tree Construction for Interconnection Network with Irregular Topologies. PDP 2003: 157-164
1990 – 1999
- 1997
- [c3]Hsin-Chou Chi, Chih-Tsung Tang:
A Deadlock-Free Routing Scheme for Interconnection Networks with Irregular Topologies. ICPADS 1997: 88-95 - 1994
- [c2]Hsin-Chou Chi, Yuval Tamir:
Starvation Prevention for Arbiters of Crossbars with Multi-Queue Input Buffers. COMPCON 1994: 292-297 - 1993
- [j1]Yuval Tamir, Hsin-Chou Chi:
Symmetric Crossbar Arbiters for VLSI Communication Switches. IEEE Trans. Parallel Distributed Syst. 4(1): 13-27 (1993) - 1991
- [c1]Hsin-Chou Chi, Yuval Tamir:
Decomposed Arbiters for Large Crossbars with Multi-Queue Input Buffers. ICCD 1991: 233-238
Coauthor Index
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