9th International Symposium on System Synthesis, ISSS '96, November 6-8, 1996, San Diego, CA, USA. IEEE Computer Society, 1996, online publication: http://computer.org/proceedings/isss/7563/7563toc.htm

Session 1: System-Level Synthesis I

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  Chunho Lee, Miodrag Potkonjak, Wayne Wolf: System-Level Synthesis of Application Specific Systems using A* Search and Generalized Force-Directed Heuristics. 2-7
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  Stephen A. Blythe, Robert A. Walker: Toward a Practical Methodology for Completely Characterizing the Optimal Design Space. 8-13
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  Johnny Öberg, Anshul Kumar, Ahmed Hemani: Grammar-Based Hardware Synthesis of Data Communication Protocols. 14-19
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  Miguel Miranda, Francky Catthoor, Martin Janssen, Hugo De Man: ADOPT: Efficient Hardware Address Generation in Distributed Memory Architectures. 20-25
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  Gernot Koch, Udo Kebschull, Wolfgang Rosenstiel: Breakpoints and Breakpoint Detection in Source Level Emulation. 26-

Session 2: High-Level Synthesis

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  Min Xu, Fadi J. Kurdahi: Layout-Driven RTL Binding Techniques for High-Level Synthesis. 33-38
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  Alan Su, Ta-Yung Liu, Yu-Chin Hsu, Mike Tien-Chien Lee: Eliminating False Loops Caused by Sharing in Control Path. 39-44
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  Michael Münch, Manfred Glesner, Norbert Wehn: An Efficient ILP-Based Scheduling Algorithm for Control-Dominated VHDL Descriptions. 45-50
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  Luiz C. V. dos Santos, Marc J. M. Heijligers, C. A. J. van Eijk, Jos T. J. van Eijndhoven, Jochen A. G. Jess: A Constructive Method for Exploiting Code Motion. 51-56
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  Luca Benini, Patrick Vuillod, Claudionor José Nunes Coelho Jr., Giovanni De Micheli: Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification. 57-

Session 3: Hardware/Software Codesign

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  Michael Gasteier, Manfred Glesner: Bus-Based Communication Synthesis on System-Level. 65-70
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  Petru Eles, Zebo Peng, Krzysztof Kuchcinski, Alex Doboli: Hardware/Software Partitioning with Iterative Improvement Heuristics. 71-76
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  Alessandro Balboni, William Fornaciari, M. Vincenzi, Donatella Sciuto: The Use of a Virtual Instruction Set for the Software Synthesis of HW/SW Embedded Systems. 77-82
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  Laurent Freund, Michel Israël, Frédéric Rousseau, J. M. Bergé, Michel Auguin, Cécile Belleudy, Guy Gogniat: A Codesign Experiment in Acoustic Echo Cancellation: GMDFa. 83-

Session 4: Programmable Processor Based Design and Synthesis

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  Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau: Memory Organization for Improved Data Cache Performance in Embedded Processors. 90-95
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  Hiroyuki Tomiyama, Hiroto Yasuura: Size-Constrained Code Placement for Cache Miss Rate Reduction. 96-104
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  Guido Araujo, Ashok Sudarsanam, Sharad Malik: Instruction Set Design and Optimizations for Address Computation in DSP Architectures. 102-107
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  Vojin Zivojnovic, Stefan Pees, C. Schälger, Markus Willems, R. Schoenen, Heinrich Meyr: DSP Processor/Compiler Co-Design: A Quantitative Approach. 108-

Session 5: System-Level Synthesis II

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  James E. Beck, Daniel P. Siewiorek: Modeling Multicomputer Task Allocation as a Vector Packing Problem. 115-120
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  Frank Vahid, Thuy Dm Le, Yu-Chin Hsu: A Comparison of Functional and Structural Partitioning. 121-126
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  Sven Wuytack, Francky Catthoor, Gjalt G. de Jong, Bill Lin, Hugo De Man: Flow Graph Balancing for Minimizing the Required Memory Bandwidth. 127-132
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  Stephen Docy, Inki Hong, Miodrag Potkonjak: Throughput Optimization in Disk-Based Real-Time Application Specific Systems. 133-138
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  Frank F. Hsu, Elizabeth M. Rudnick, Janak H. Patel: Testability Insertion in Behavioral Descriptions. 139-144