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ORCID17th HPCA 2011: San Antonio, Texas, USA
- 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), February 12-16 2011, San Antonio, Texas, USA. IEEE Computer Society 2011, ISBN 978-1-4244-9432-3
Keynote
- James R. Larus:
Programming the cloud. 1
Multithreading and Multicores
- Krishna K. Rangan, Michael D. Powell, Gu-Yeon Wei, David M. Brooks:
Achieving uniform performance and maximizing throughput in the presence of heterogeneity. 3-14 - Rakesh Ranjan, Fernando Latorre, Pedro Marcuello, Antonio González
:
Fg-STP: Fine-Grain Single Thread Partitioning on Multicores. 15-24 - Wilson W. L. Fung, Tor M. Aamodt:
Thread block compaction for efficient SIMT control flow. 25-36
Caches and TLB
- Hamid Reza Ghasemi, Stark C. Draper, Nam Sung Kim:
Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors. 38-49 - Clinton Wills Smullen IV, Vidyabhushan Mohan, Anurag Nigam, Sudhanva Gurumurthi, Mircea R. Stan:
Relaxing non-volatility for fast and energy-efficient STT-RAM caches. 50-61 - Abhishek Bhattacharjee, Daniel Lustig, Margaret Martonosi:
Shared last-level TLBs for chip multiprocessors. 62-63
Multicores
- Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge:
Bloom Filter Guided Transaction Scheduling. 75-86 - Mojtaba Mehrara, Po-Chun Hsu, Mehrzad Samadi, Scott A. Mahlke:
Dynamic parallelization of JavaScript applications using an ultra-lightweight speculation mechanism. 87-98 - Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tuck:
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor. 99-110 - Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Sun:
MOPED: Orchestrating interprocess message data on CMPs. 111-120
Interconnection Networks
- Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
Addressing system-level trimming issues in on-chip nanophotonic networks. 122-131 - Dana Vantrease, Mikko H. Lipasti, Nathan L. Binkert:
Atomic Coherence: Leveraging nanophotonics to build race-free cache coherence protocols. 132-143 - Chris Fallin, Chris Craik, Onur Mutlu:
CHIPPER: A low-complexity bufferless deflection router. 144-155 - Jian Li, Wei Huang, Charles Lefurgy, Lixin Zhang, Wolfgang E. Denzel, Richard R. Treumann, Kun Wang:
Power shifting in Thrifty Interconnection Network. 156-167
Best Student Paper Session
- Michael Ferdman, Pejman Lotfi-Kamran, Ken Balet, Babak Falsafi:
Cuckoo directory: A scalable directory for many-core systems. 169-180 - Hung-Wei Tseng, Dean M. Tullsen:
Data-triggered threads: Eliminating redundant computation. 181-192 - Jeffery A. Brown, Leo Porter, Dean M. Tullsen:
Fast thread migration via cache working set prediction. 193-204 - Chao Li, Wangyuan Zhang, Chang-Burm Cho, Tao Li:
SolarCore: Solar energy driven multi-core architecture power management. 205-216
Keynote
- Kathryn S. McKinley:
How's the parallel computing revolution going? 217
Multicore Caches
- Hyunjin Lee, Sangyeun Cho, Bruce R. Childers:
CloudCache: Expanding and shrinking private caches. 219-230 - Shekhar Srikantaiah, Emre Kultursay, Tao Zhang, Mahmut T. Kandemir, Mary Jane Irwin, Yuan Xie:
MorphCache: A Reconfigurable Adaptive Multi-level Cache hierarchy. 231-242 - R. Manikantan, Kaushik Rajan, R. Govindarajan:
NUcache: An efficient multicore cache organization based on Next-Use distance. 243-253
I/O
- Guangdeng Liao, Xia Zhu, Laxmi N. Bhuyan:
A new server I/O architecture for high speed networks. 255-265 - Feng Chen, Rubao Lee, Xiaodong Zhang:
Essential roles of exploiting internal parallelism of flash memory based solid state drives in high-speed data processing. 266-277 - Qing Yang, Jin Ren:
I-CASH: Intelligently Coupled Array of SSD and HDD. 278-289
Industrial Paper Session
- Niti Madan, Alper Buyuktosunoglu, Pradip Bose, Murali Annavaram:
A case for guarded power gating for multi-core processors. 291-300 - Xiangyong Ouyang, David W. Nellans, Robert Wipfel, David Flynn, Dhabaleswar K. Panda:
Beyond block I/O: Rethinking traditional storage primitives. 301-311 - Rui Hou, Lixin Zhang, Michael C. Huang, Kun Wang, Hubertus Franke, Yi Ge, Xiaotao Chang:
Efficient data streaming with on-chip accelerators: Opportunities and challenges. 312-320 - Javier Carretero, Xavier Vera, Jaume Abella, Tanausú Ramírez, Matteo Monchiero, Antonio González:
Hardware/software-based diagnosis of load-store queues using expandable activity logs. 321-331
Memory Models & Memory Systems
- Derek Hower, Polina Dudnik, Mark D. Hill, David A. Wood:
Calvin: Deterministic or not? Free will to choose. 333-334 - Madhura Joshi, Wangyuan Zhang, Tao Li:
Mercury: A fast and energy-efficient multi-level cell based Phase Change Memory system. 345-356 - Dongyoon Lee, Mahmoud Said, Satish Narayanasamy, Zijiang Yang:
Offline symbolic analysis to infer Total Store Order. 357-358 - Jayaram Bobba, Marc Lupon, Mark D. Hill, David A. Wood:
Safe and efficient supervised memory systems. 369-380
Modeling & Simulation
- Yao Zhang, John D. Owens:
A quantitative performance analysis model for GPU architectures. 382-393 - Hans M. Jacobson, Alper Buyuktosunoglu, Pradip Bose, Emrah Acar, Richard J. Eickemeyer:
Abstraction and microarchitecture scaling in early-stage power modeling. 394-405 - Michael Pellauer, Michael Adler, Michel A. Kinsy, Angshuman Parashar, Joel S. Emer:
HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing. 406-417
Uniprocessors
- Owen Anderson, Emily Fortuna, Luis Ceze, Susan J. Eggers:
Checked Load: Architectural support for JavaScript type-checking on mobile processors. 419-430 - Behnam Robatmili, Madhu Saravana Sibi Govindan, Doug Burger, Stephen W. Keckler:
Exploiting criticality to reduce bottlenecks in distributed uniprocessors. 431-442 - André Seznec:
Storage free confidence estimation for the TAGE branch predictor. 443-454
Survivabililty, Reliability, and Security
- Xiaowei Jiang, Yan Solihin:
Architectural framework for supporting operating system survivability. 456-465 - Doe Hyun Yoon, Naveen Muralimanohar, Jichuan Chang, Parthasarathy Ranganathan, Norman P. Jouppi, Mattan Erez:
FREE-p: Protecting non-volatile memory against both hard and soft errors. 466-477 - Moinuddin K. Qureshi, André Seznec, Luis A. Lastras, Michele Franceschini:
Practical and secure PCM systems by online detection of malicious write streams. 478-489
Power & Thermal Management
- Jack Sampson, Ganesh Venkatesh, Nathan Goulding-Hotta, Saturnino Garcia, Steven Swanson, Michael Bedford Taylor:
Efficient complex operators for irregular codes. 491-502 - Venkatraman Govindaraju, Chen-Han Ho, Karthikeyan Sankaralingam:
Dynamically Specialized Datapaths for energy efficient computing. 503-514 - Song Liu, Brian Leung, Alexander Neckar, Seda Ogrenci Memik, Gokhan Memik, Nikos Hardavellas:
Hardware/software techniques for DRAM thermal management. 515-525
Asymmetric & Polymorphic Caches
- Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishankar R. Iyer, Zhen Fang, Sadagopan Srinivasan, Srihari Makineni, Paul Brett, Chita R. Das:
ACCESS: Smart scheduling for asymmetric cache CMPs. 527-538 - Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke:
Archipelago: A polymorphic cache design for enabling robust near-threshold operation. 539-550
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