17. HPCA 2011:
San Antonio,
Texas,
USA
17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), February 12-16 2011, San Antonio, Texas, USA.
IEEE Computer Society 2011
Keynote
Multithreading and Multicores
Caches and TLB
Multicores
- Geoffrey Blake, Ronald G. Dreslinski, Trevor N. Mudge:
Bloom Filter Guided Transaction Scheduling.
75-86
- Mojtaba Mehrara, Po-Chun Hsu, Mehrzad Samadi, Scott A. Mahlke:
Dynamic parallelization of JavaScript applications using an ultra-lightweight speculation mechanism.
87-98
- Sanghoon Lee, Devesh Tiwari, Yan Solihin, James Tuck:
HAQu: Hardware-accelerated queueing for fine-grained threading on a chip multiprocessor.
99-110
- Junli Gu, Steven S. Lumetta, Rakesh Kumar, Yihe Sun:
MOPED: Orchestrating interprocess message data on CMPs.
111-120
Interconnection Networks
- Christopher Nitta, Matthew K. Farrens, Venkatesh Akella:
Addressing system-level trimming issues in on-chip nanophotonic networks.
122-131
- Dana Vantrease, Mikko H. Lipasti, Nathan L. Binkert:
Atomic Coherence: Leveraging nanophotonics to build race-free cache coherence protocols.
132-143
- Chris Fallin, Chris Craik, Onur Mutlu:
CHIPPER: A low-complexity bufferless deflection router.
144-155
- Jian Li, Wei Huang, Charles Lefurgy, Lixin Zhang, Wolfgang E. Denzel, Richard R. Treumann, Kun Wang:
Power shifting in Thrifty Interconnection Network.
156-167
Best Student Paper Session
Keynote
Multicore Caches
I/O
Industrial Paper Session
- Niti Madan, Alper Buyuktosunoglu, Pradip Bose, Murali Annavaram:
A case for guarded power gating for multi-core processors.
291-300
- Xiangyong Ouyang, David W. Nellans, Robert Wipfel, David Flynn, Dhabaleswar K. Panda:
Beyond block I/O: Rethinking traditional storage primitives.
301-311
- Rui Hou, Lixin Zhang, Michael C. Huang, Kun Wang, Hubertus Franke, Yi Ge, Xiaotao Chang:
Efficient data streaming with on-chip accelerators: Opportunities and challenges.
312-320
- Javier Carretero, Xavier Vera, Jaume Abella, Tanausu Ramirez, Matteo Monchiero, Antonio González:
Hardware/software-based diagnosis of load-store queues using expandable activity logs.
321-331
Memory Models & Memory Systems
- Derek Hower, Polina Dudnik, Mark D. Hill, David A. Wood:
Calvin: Deterministic or not? Free will to choose.
333-334
- Madhura Joshi, Wangyuan Zhang, Tao Li:
Mercury: A fast and energy-efficient multi-level cell based Phase Change Memory system.
345-356
- Dongyoon Lee, Mahmoud Said, Satish Narayanasamy, Zijiang Yang:
Offline symbolic analysis to infer Total Store Order.
357-358
- Jayaram Bobba, Marc Lupon, Mark D. Hill, David A. Wood:
Safe and efficient supervised memory systems.
369-380
Modeling & Simulation
Uniprocessors
Survivabililty,
Reliability,
and Security
Power & Thermal Management
- Jack Sampson, Ganesh Venkatesh, Nathan Goulding-Hotta, Saturnino Garcia, Steven Swanson, Michael Bedford Taylor:
Efficient complex operators for irregular codes.
491-502
- Venkatraman Govindaraju, Chen-Han Ho, Karthikeyan Sankaralingam:
Dynamically Specialized Datapaths for energy efficient computing.
503-514
- Song Liu, Brian Leung, Alexander Neckar, Seda Ogrenci Memik, Gokhan Memik, Nikos Hardavellas:
Hardware/software techniques for DRAM thermal management.
515-525
Asymmetric & Polymorphic Caches
- Xiaowei Jiang, Asit K. Mishra, Li Zhao, Ravishankar Iyer, Zhen Fang, Sadagopan Srinivasan, Srihari Makineni, Paul Brett, Chita R. Das:
ACCESS: Smart scheduling for asymmetric cache CMPs.
527-538
- Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott A. Mahlke:
Archipelago: A polymorphic cache design for enabling robust near-threshold operation.
539-550
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