9. HPCA 2003: Anaheim, California, USA
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), Anaheim, California, USA, February 8-12, 2003. IEEE Computer Society 2003 ISBN 0-7695-1871-0
Keynote Speaker
Dileep Bhandarkar: Billion Transistor Chips in Mainstream Enterprise Platforms of the Future. 3
Multithreading
Alaa R. Alameldeen, David A. Wood: Variability in Architectural Simulations of Multi-Threaded Workloads. 7-18
Joshua Redstone, Susan J. Eggers, Henry M. Levy: Mini-Threads: Increasing TLP on Small-Scale SMT Processors. 19-30
Ali El-Moursy, David H. Albonesi: Front-End Policies for Improved Issue Efficiency in SMT Processors. 31-40
Branch Prediction
Daniel A. Jiménez: Reconsidering Complex Branch Predictors. 43-52
Beth Simon, Brad Calder, Jeanne Ferrante: Incorporating Predicate Information into Branch Predictors. 53-64
Lei Chen, Steve Dropsho, David H. Albonesi: Dynamic Data Dependence Tracking and its Application to Branch Prediction. 65-76
Power Efficient Designs
Russ Joseph, David Brooks, Margaret Martonosi: Control Techniques to Eliminate Voltage Emergencies in High Performance Processors. 79-90
Li Shang, Li-Shiuan Peh, Niraj K. Jha: Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. 91-102
Juan L. Aragón, José González, Antonio González: Power-Aware Control Speculation through Selective Throttling. 103-112
Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykumar, Kaushik Roy: Deterministic Clock Gating for Microprocessor Power Reduction. 113-122
Keynote Speaker
Eric Kronstadt: Beyond Performance: Some (Other) Challenges for Systems Design. 125
Superscalars
Onur Mutlu, Jared Stark, Chris Wilkerson, Yale N. Patt: Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors. 129-140
Mariko Sakamoto, Akira Katsuno, Aiichiro Inoue, Takeo Asakawa, Haruhiko Ueno, Kuniki Morita, Yasunori Kimura: Microarchitecture and Performance Analysis of a SPARC-V9 Microprocessor for Enterprise Server Systems. 141-152
Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens, Brian Towles: Exploring the VLSI Scalability of Stream Processors. 153-164
Brian Slechta, David Crowe, Brian Fahs, Michael Fertig, Gregory A. Muthler, Justin Quek, Francesco Spadini, Sanjay J. Patel, Steven Lumetta: Dynamic Optimization of Micro-Operations. 165-176
Multiprocessor Systems
Khaled Z. Ibrahim, Gregory T. Byrd, Eric Rotenberg: Slipstream Execution Mode for CMP-Based Multiprocessors. 179-190
María Jesús Garzarán, Milos Prvulovic, José María Llabería, Víctor Viñals, Lawrence Rauchwerger, Josep Torrellas: Tradeoffs in Buffering Memory State for Thread-Level Speculation in Multiprocessors. 191-202
Rosalia Christodoulopoulou, Reza Azimi, Angelos Bilas: Dynamic Data Replication: An Approach to Providing Fault-Tolerant Shared Memory Clusters. 203-214
Memory and Communication Performance
Martin Karlsson, Kevin E. Moore, Erik Hagersten, David A. Wood: Memory System Behavior of Java-Based Middleware. 217-228
Kiran Nagaraja, Neeraj Krishnan, Ricardo Bianchini, Richard P. Martin, Thu D. Nguyen: Evaluating the Impact of Communication Architecture on the Performability of Cluster-Based Services. 229-240
Zoran Radovic, Erik Hagersten: Hierarchical Backoff Locks for Nonuniform Communication Architectures. 241-252
Eun Jung Kim, Ki Hwan Yum, Chita R. Das, Mazin S. Yousif, José Duato: Performance Enhancement Techniques for InfiniBand? Architecture. 253-262
Keynote Speake
Peter M. Kogge: The State of State. 266
Profiling and Simulation Support
Satish Narayanasamy, Timothy Sherwood, Suleyman Sair, Brad Calder, George Varghese: Catching Accurate Profiles in Hardwar. 269-280
Joshua J. Yi, David J. Lilja, Douglas M. Hawkins: A Statistically Rigorous Approach for Improving Simulation Methodology. 281-291
Caching and Prefetching
Blaise Gassend, G. Edward Suh, Dwaine E. Clarke, Marten van Dijk, Srinivas Devadas: Caches and Hash Trees for Efficient Memory Integrity Verification. 295-306
Gokhan Memik, Glenn Reinman, William H. Mangione-Smith: Just Say No: Benefits of Early Cache Miss Determinatio. 307-316

Networks and Communication
Michael Bedford Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal: Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture. 341-353
Andrei Terechko, Erwan Le Thenaff, Manish Garg, Jos T. J. van Eijndhoven, Henk Corporaal: Inter-Cluster Communication Models for Clustered VLIW Processors. 354-364
Wai Hong Ho, Timothy Mark Pinkston: A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns. 377-388



