10. ACM Great Lakes Symposium on VLSI 2000: Chicago, Illinois, USA

@proceedings{DBLP:conf/glvlsi/2000,
  editor    = {Majid Sarrafzadeh and
               Prithviraj Banerjee and
               Kaushik Roy},
  title     = {Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000,
               Chicago, Illinois, USA, March 2-4, 2000},
  booktitle = {ACM Great Lakes Symposium on VLSI},
  publisher = {ACM},
  year      = {2000},
  isbn      = {1-58113-251-4},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

• Vivek De, Shekhar Borkar:
  Low power and high performance design challenges in future technologies. 1-6
  
• Azeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl:
  CMOS system-on-a-chip voltage scaling beyond 50nm. 7-12
  
• Vijay Sundararajan, Keshab K. Parhi:
  Reducing bus transition activity by limited weight coding with codeword slimming. 13-16
  
• Luca Benini, Marco Ferrero, Alberto Macii, Enrico Macii, Massimo Poncino:
  Supporting system-level power exploration for DSP applications. 17-22
  
• V. K. Pisini, Sofiène Tahar, Paul Curzon, Otmane Aït Mohamed, Xiaoyu Song:
  Formal hardware verification by integrating HOL and MDG. 23-28
  
• Salvador Mir, Benoît Charlot, Gabriela Nicolescu, Philippe Coste, Fabien Parrain, Nacer-Eddine Zergainoh, Bernard Courtois, Ahmed Amine Jerraya, Márta Rencz:
  Towards design and validation of mixed-technology SOCs. 29-33
  
• Jennifer L. White, Anthony S. Wojcik, Moon-Jung Chung, Travis E. Doom:
  Candidate subcircuits for functional module identification in logic circuits. 34-38
  
• Christoph Meinel, Christian Stangier:
  Speeding up symbolic model checking by accelerating dynamic variable reordering. 39-42
  
• Sandro Wefel, Paul Molitor:
  Prove that a faulty multiplier is faulty!? 43-46
  
• Cheng-Kok Koh, Patrick H. Madden:
  Manhattan or non-Manhattan?: a study of alternative VLSI routing architectures. 47-52
  
• Sudhakar Bobba, Ibrahim N. Hajj:
  High-performance bidirectional repeaters. 53-58
  
• Tom W. Chen, Alkan Cengiz:
  Measuring routing congestion for multi-layer global routing. 59-62
  
• Radu M. Secareanu, Eby G. Friedman:
  Transparent repeaters. 63-66
  
• José G. Delgado-Frias, Jabulani Nyathi, Laxmi N. Bhuyan:
  A wave-pipelined router architecture using ternary associative memory. 67-70
  
• Bharat Krishna, C. Y. Roger Chen, Naresh Sehgal:
  A novel technique for sea of gates global routing. 71-74
  
• David Blaauw, Kaushik Gala, Vladimir Zolotov, Rajendran Panda, Junfeng Wang:
  On-chip inductance modeling. 75-80
  
• R. Venkatraman, Lalit M. Patnaik:
  An evolutionary approach to timing driven FPGA placement. 81-85
  
• Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee:
  Parallel algorithms for FPGA placement. 86-94
  
• Kia Bazargan, Abhishek Ranjan, Majid Sarrafzadeh:
  Fast and accurate estimation of floorplans in logic/high-level synthesis. 95-100
  
• George Gristede, Wei Hwang:
  A comparison of dual-rail pass transistor logic families in 1.5V, 0.18µm CMOS technology for low power applications. 101-106
  
• Hendrawan Soeleman, Kaushik Roy:
  Digital CMOS logic operation in the sub-threshold region. 107-112
  
• A. E. Hussein, Mohamed I. Elmasry:
  Low power high speed analog-to-digital converter for wireless communications. 113-116
  
• Jeyran Hezavei, Narayanan Vijaykrishnan, Mary Jane Irwin:
  A comparative study of power efficient SRAM designs. 117-122
  
• Virgil Andronache, Edwin Hsing-Mean Sha, Nelson L. Passos:
  Design and analysis of efficient application-specific on-line page replacement techniques. 123-128
  
• Helvio P. Peixoto, Margarida F. Jacome:
  A new technique for estimating lower bounds on latency for high level synthesis. 129-132
  
• Bo-Sung Kim, Jun Dong Cho:
  Maximizing memory data reuse for lower power motion estimation. 133-138
  
• Chantana Chantrapornchai, Edwin Hsing-Mean Sha, Xiaobo Hu:
  Efficient algorithms for acceptable design exploration. 139-142
  
• Qiao Li, Sung-Mo Kang:
  Technology independent arbitrary device extractor. 143-146
  
• Luca Benini, Alessandro Bogliolo, Enrico Macii, Massimo Poncino, Mihai Surmei:
  Regression-based RTL power models for controllers. 147-152
  
• Bibhudatta Sahoo, Martin Kuhlmann, Keshab K. Parhi:
  A low-power correlator. 153-155
  
• Ki-Seok Chung, Taewhan Kim, Chien-Liang Liu:
  Behavioral-level partitioning for low power design in control-dominated application. 156-161
  
• Hung-Jung Chen, Bradley S. Carlson:
  Power estimation for a submicron CMOS inverter driving a CRC interconnect load. 162-166
  
• Gary L. Dare, Charles A. Zukowski:
  Accuracy management for mixed-mode digital VLSI simulation. 167-170
  
• Kevin T. Tang, Eby G. Friedman:
  Noise estimation due to signal activity for capacitively coupled CMOS logic gates. 171-176
  
• Benjamin Bishop, Thomas P. Kelliher, Mary Jane Irwin:
  SPARTA: Simulation of Physics on a Real-Time Architecture. 177-182
  
• Qiao Li, Sung-Mo Kang:
  Efficient algorithms for polygon to trapezoid decomposition and trapezoid corner stitching. 183-188
  
• Craig Beebe, Jo Dale Carothers, Alfonso Ortega:
  MCM placement using a realistic thermal model. 189-192
  
• Bill Halpin, C. Y. Roger Chen, Naresh Sehgal:
  A sensitivity based placer for standard cells. 193-196
  

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