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Publication search results
found 94 matches
- 1995
- Hans Achatz:
Generating several solutions for the scheduling problem in high-level synthesis. EURO-DAC 1995: 66-71 - Karlheinz Agsteiner, Dieter Monjau, Sören Schulze:
Object-oriented high-level modeling of system components for the generation of VHDL code. EURO-DAC 1995: 436-441 - Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins:
Performance-oriented placement and routing for field-programmable gate arrays. EURO-DAC 1995: 80-85 - Jan Andersson:
A DSP ASIC design flow based on VHDL and ASIC-emulation. EURO-DAC 1995: 562-567 - Laurent Arditi, Hélène Collavizza:
Towards verifying VHDL descriptions of processors. EURO-DAC 1995: 414-419 - Smita Bakshi, Daniel D. Gajski:
A memory selection algorithm for high-performance pipelines. EURO-DAC 1995: 124-129 - Thomas Benner, Rolf Ernst, Achim Österling:
Scalable performance scheduling for hardware-software cosynthesis. EURO-DAC 1995: 164-169 - Ansgar Bredenfeld:
Cooperative concurrency control for design environments. EURO-DAC 1995: 308-313 - Peter T. Breuer, Natividad Martínez Madrid:
A native process algebra for VHDL. EURO-DAC 1995: 420-426 - Naveen Buddi, Malgorzata Chrzanowska-Jeske, Charles L. Saxe:
Layout synthesis for datapath designs. EURO-DAC 1995: 86-90 - Gerhard H. Büttner:
Setting up a retrieval system for design reuse - experiences and acceptance. EURO-DAC 1995: 575-578 - Gianpiero Cabodi, Stefano Quer, Paolo Camurati:
Computing subsets of equivalence classes for large FSMs. EURO-DAC 1995: 288-293 - Srimat T. Chakradhar, Anand Raghunathan:
Bottleneck removal algorithm for dynamic compaction and test cycles reduction. EURO-DAC 1995: 98-104 - Peter Conradi:
Information model of a compound graph representation for system and architecture level design. EURO-DAC 1995: 22-27 - Jerzy J. Dabrowski:
Functional-level analog macromodeling with piecewise linear signals. EURO-DAC 1995: 222-227 - Jean Michel Daga, Michel Robert, Daniel Auvergne:
Delay modelling improvement for low voltage applications. EURO-DAC 1995: 216-221 - Vladimir B. Dmitriev-Zdorov, Bernhard Klaassen:
An improved relaxation approach for mixed system analysis with several simulation tools. EURO-DAC 1995: 274-279 - Andrew A. Duncan, David C. Hendry:
Area efficient DSP datapath synthesis. EURO-DAC 1995: 130-135 - Wolfgang Ecker:
Semi-dynamic scheduling of synchronization-mechanisms. EURO-DAC 1995: 374-379 - Wolfgang Ecker:
A classification of design steps and their verification. EURO-DAC 1995: 536-541 - Wolfgang Ecker, Manfred Huber:
VHDL-based communication and synchronization synthesis. EURO-DAC 1995: 458-462 - Petru Eles, Krzysztof Kuchcinski, Zebo Peng, Alexa Doboli:
Timing constraint specification and synthesis in behavioral VHDL. EURO-DAC 1995: 452-457 - Armin Englmaier:
Mesh current method for computing the current distribution in planar conductor surfaces and possible applications in circuit simulation. EURO-DAC 1995: 348-353 - Carol A. Fields:
Creating hierarchy in HDL-based high density FGPA design. EURO-DAC 1995: 594-599 - Andrea Finotello, Maurizio Paolini:
The VHDL based design of the MIDA MPEG1 audio decoder. EURO-DAC 1995: 579-584 - J. Forrest:
ODE: output direct state machine encoding. EURO-DAC 1995: 600-605 - Franco Fummi, U. Rovati, Donatella Sciuto:
Testable synthesis of high complex control devices. EURO-DAC 1995: 117-122 - Thomas Gabler, Sabine März-Rössel:
An approach to guided incremental specification. EURO-DAC 1995: 368-373 - D. Galán, Carlos Jesús Jiménez-Fernández, Angel Barriga, Santiago Sánchez-Solano:
VHDL package for description of fuzzy logic controllers. EURO-DAC 1995: 528-533 - Cristian A. Giumale, Hilary J. Kahn:
A core information model of VHDL. EURO-DAC 1995: 28-33
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