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ORCIDJoseph L. Ganley
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2000 – 2009
- 2008
[r1]Steve Teig, Asmus Hetzel, Joseph L. Ganley, Jon Frankle, Aki Fujimura:
X Architecture Place and Route. Handbook of Algorithms for Physical Design Automation 2008- 2001
- [j15]Joseph L. Ganley, Lenwood S. Heath:
The pagenumber of k-trees is O(k). Discret. Appl. Math. 109(3): 215-221 (2001) - 2000
- [j14]Ion I. Mandoiu
, Vijay V. Vazirani, Joseph L. Ganley:
A new heuristic for rectilinear Steiner trees. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(10): 1129-1139 (2000)
1990 – 1999
- 1999
- [j13]Joseph L. Ganley:
Computing Optimal Rectilinear Steiner Trees: A Survey and Experimental Evaluation. Discret. Appl. Math. 90(1-3): 161-171 (1999) - [j12]Joseph L. Ganley, James P. Cohoon:
Provably good moat routing. Integr. 27(1): 47-56 (1999) - [c10]Ion I. Mandoiu, Vijay V. Vazirani, Joseph L. Ganley:
A new heuristic for rectilinear Steiner trees. ICCAD 1999: 157-162 - [c9]Joseph L. Ganley:
Efficient solution of systems of orientation constraints. ISPD 1999: 140-144 - 1998
- [j11]Joseph L. Ganley, Lenwood S. Heath:
An Experimental Evaluation of Local Search Heuristics for Graph Partitioning. Computing 60(2): 121-132 (1998) - [j10]Joseph L. Ganley, Jeffrey S. Salowe:
The Power-p Steiner Tree Problem. Nord. J. Comput. 5(2): 115-127 (1998) - [j9]Tamra Carpenter, Steven Cosares, Joseph L. Ganley, Iraj Saniee:
A Simple Approximation Algorithm for Two Problems in Circuit Design. IEEE Trans. Computers 47(11): 1310-1312 (1998) - [j8]Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins:
Placement and Routing for Performance-Oriented FPGA Layout. VLSI Design 7(1): 97-110 (1998) - 1997
- [j7]Joseph L. Ganley, James P. Cohoon:
Improved Computation of Optimal Rectilinear Steiner Minimal Trees. Int. J. Comput. Geom. Appl. 7(5): 457-472 (1997) - [j6]Joseph L. Ganley:
Accuracy and fidelity of fast net length estimates. Integr. 23(2): 151-155 (1997) - [j5]Joseph L. Ganley, James P. Cohoon:
Minimum-Congestion Hypergraph Embedding in a Cycle. IEEE Trans. Computers 46(5): 600-602 (1997) - 1996
- [j4]Joseph L. Ganley, Jeffrey S. Salowe:
Optimal and approximate bottleneck Steiner trees. Oper. Res. Lett. 19(5): 217-224 (1996) - [j3]Joseph L. Ganley, James P. Cohoon:
Rectilinear Steiner trees on a checkerboard. ACM Trans. Design Autom. Electr. Syst. 1(4): 512-522 (1996) - [c8]Joseph L. Ganley, James P. Cohoon:
A Provably Good Moat Routing Algorithm. Great Lakes Symposium on VLSI 1996: 86-85 - 1995
- [c7]Joseph L. Ganley, Mordecai J. Golin, Jeffrey S. Salowe:
The Multi-Weighted Spanning Tree Problem (Extended Abstract). COCOON 1995: 141-150 - [c6]Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins:
Performance-oriented placement and routing for field-programmable gate arrays. EURO-DAC 1995: 80-85 - [c5]Joseph L. Ganley, James P. Cohoon:
Thumbnail rectilinear Steiner trees. Great Lakes Symposium on VLSI 1995: 46-49 - 1994
- [j2]Joseph L. Ganley, Lenwood S. Heath:
Optimal and Random Partitions of Random Graphs. Comput. J. 37(7): 641-643 (1994) - [j1]Joseph L. Ganley, Lenwood S. Heath:
Heuristics for laying out information graphs. Computing 52(4): 389-405 (1994) - [c4]Joseph L. Ganley, James P. Cohoon:
Optimal Rectilinear Steiner Minimal Trees in O (n22.62n) Time. CCCG 1994: 308-313 - [c3]Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins:
An architecture-independent approach to FPGA routing based on multi-weighted graphs. EURO-DAC 1994: 259-264 - [c2]Joseph L. Ganley, James P. Cohoon:
A faster dynamic programming algorithm for exact rectilinear Steiner minimal trees. Great Lakes Symposium on VLSI 1994: 238-241 - [c1]Joseph L. Ganley, James P. Cohoon:
Routing a Multi-Terminal Critical Net: Steiner Tree Construction in the Presence of Obstacles. ISCAS 1994: 113-116
Coauthor Index
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