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Publication search results
found 133 matches
- 2002
- Emrah Acar, Florentin Dartu, Lawrence T. Pileggi:
TETA: transistor-level waveform evaluation for timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(5): 605-616 (2002) - Cagdas Akturan, Margarida F. Jacome:
RS-FDRA: A register-sensitive software pipelining algorithm for embedded VLIW processors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1395-1415 (2002) - Cesare Alippi:
A probably approximately correct framework to estimate performancedegradation in embedded systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7): 749-762 (2002) - Charles J. Alpert, Anirudh Devgan, John P. Fishburn, Stephen T. Quay:
Correction to "interconnect synthesis without wire tapering". IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 497-497 (2002) - Kaustav Banerjee, Amit Mehrotra:
Analysis of on-chip inductance effects for distributed RLC interconnects. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8): 904-915 (2002) - Reinaldo A. Bergamaschi:
Bridging the domains of high-level and logic synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(5): 582-596 (2002) - Bhargab B. Bhattacharya, Alexej Dmitriev, Michael Gössel, Krishnendu Chakrabarty:
Synthesis of single-output space compactors for scan-based sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1171-1179 (2002) - David T. Blaauw, Vladimir Zolotov, Savithri Sundareswaran:
Slope propagation in static timing analysis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1180-1195 (2002) - Carlo Brandolese, Fabio Salice, William Fornaciari, Donatella Sciuto:
Static power modeling of 32-bit microprocessors. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11): 1306-1316 (2002) - Steven C. Chan, Kenneth L. Shepard, Dae-Jin Kim:
Static noise analysis for digital integrated circuits in partially depleted silicon-on-insulator technology. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8): 916-927 (2002) - Anshuman Chandra, Krishnendu Chakrabarty:
Low-power scan testing and test data compression forsystem-on-a-chip. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(5): 597-604 (2002) - Anshuman Chandra, Krishnendu Chakrabarty:
Test data compression and decompression based on internal scanchains and Golomb coding. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(6): 715-722 (2002) - Wei-Yu Chen, Sandeep K. Gupta, Melvin A. Breuer:
Analytical models for crosstalk excitation and propagation in VLSI circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1117-1131 (2002) - Yu Chen, Andrew B. Kahng, Gabriel Robins, Alexander Zelikovsky:
Area fill synthesis for uniform layout density. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(10): 1132-1147 (2002) - Chunhong Chen, Xiaojian Yang, Majid Sarrafzadeh:
Predicting potential performance for digital circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3): 253-262 (2002) - Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu:
Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(11): 1328-1336 (2002) - Yih-Chih Chou, Youn-Long Lin:
Effective enforcement of path-delay constraints inperformance-driven placement. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1): 15-22 (2002) - Eui-Young Chung, Luca Benini, Giovanni De Micheli, Gabriele Luculli, Marco Carilli:
Value-sensitive automatic code specialization for embedded software. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(9): 1051-1067 (2002) - Maciej J. Ciesielski, Serkan Askar, Samuel Levitin:
Analytical approach to layout generation of datapath cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1480-1488 (2002) - Jason Cong, David Zhigang Pan:
Wire width planning for interconnect performance optimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3): 319-329 (2002) - Jordi Cortadella, Michael Kishinevsky, Steven M. Burns, Alex Kondratyev, Luciano Lavagno, Ken S. Stevens, Alexander Taubin, Alexandre Yakovlev:
Lazy transition systems and asynchronous circuit synthesis withrelative timing assumptions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 109-130 (2002) - Paolo Crippa, Claudio Turchetti, Massimo Conti:
A statistical methodology for the design of high-performance CMOScurrent-steering digital-to-analog converters. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 377-394 (2002) - Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen:
Circuit simplification for the symbolic analysis of analogintegrated circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 395-407 (2002) - Sabyasachi Das, Sunil P. Khatri:
An efficient and regular routing methodology for datapath designsusing net regularity extraction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(1): 93-101 (2002) - Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky:
Provably good global buffering by generalized multiterminalmulticommodity flow approximation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(3): 263-274 (2002) - Stephen A. Edwards:
An Esterel compiler for large control-dominated systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(2): 169-183 (2002) - Yungseon Eo, Jongin Shim, William R. Eisenstadt:
A traveling-wave-based waveform approximation technique for thetiming verification of single transmission lines. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(6): 723-730 (2002) - Yungseon Eo, Seongkyun Shin, William R. Eisenstadt, Jongin Shim:
Generalized traveling-wave-based waveform approximation technique for the efficient signal integrity verification of multicoupled transmission line system. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(12): 1489-1497 (2002) - Nestoras E. Evmorfopoulos, Georgios I. Stamoulis, John N. Avaritsiotis:
A Monte Carlo approach for maximum power estimation based onextreme value theory. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(4): 415-432 (2002) - Michele Favalli, Marcello Dalpasso:
Bridging fault modeling and simulation for deep submicron CMOS ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(8): 941-953 (2002)
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