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Publication search results
found 152 matches
- 1995
- Vishwani D. Agrawal, Srimat T. Chakradhar:
Combinational ATPG theorems for identifying untestable faults in sequential circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1155-1160 (1995) - Charles J. Alpert, T. C. Hu, Dennis J.-H. Huang, Andrew B. Kahng, David R. Karger:
Prim-Dijkstra tradeoffs for improved performance-driven routing tree design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(7): 890-896 (1995) - Charles J. Alpert, Andrew B. Kahng:
Multiway partitioning via geometric embeddings, orderings, and dynamic programming. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11): 1342-1358 (1995) - Pranav Ashar, Sujit Dey, Sharad Malik:
Exploiting multicycle false paths in the performance optimization of sequential logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1067-1075 (1995) - Pranav Ashar, Sharad Malik:
Functional timing analysis using ATPG. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(8): 1025-1030 (1995) - Bernd Becker, Rolf Drechsler, Paul Molitor:
On the generation of area-time optimal testable adders. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1049-1066 (1995) - Kenneth D. Boese, Andrew B. Kahng, Bernard A. McCoy, Gabriel Robins:
Near-optimal critical sink routing tree constructions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1417-1436 (1995) - Steven Bova, Graham F. Carey:
A Taylor-Galerkin finite element method for the hydrodynamic semiconductor equations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1437-1444 (1995) - Elizabeth J. Brauer, Sung-Mo Kang:
An algorithm for functional verification of digital ECL circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1546-1556 (1995) - Jay B. Brockman, Stephen W. Director:
The schema-based approach to workflow management. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(10): 1257-1267 (1995) - Bradley S. Carlson, Suh-Juch Lee:
Delay optimization of digital CMOS VLSI circuits by transistor reordering. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(10): 1183-1192 (1995) - Srimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal:
Energy models for delay testing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(6): 728-739 (1995) - Anantha P. Chandrakasan, Miodrag Potkonjak, Renu Mehra, Jan M. Rabaey, Robert W. Brodersen:
Optimizing power using transformations. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(1): 12-31 (1995) - Chuan-Hua Chang, Edward S. Davidson, Karem A. Sakallah:
Maximum rate single-phase clocking of a closed pipeline including wave pipelining, stoppability, and startability. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1526-1545 (1995) - Jau-Shien Chang, Chen-Shang Lin:
Test set compaction for combinational circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(11): 1370-1378 (1995) - Abhijit Chatterjee, Charles F. Machala III, Ping Yang:
A submicron DC MOSFET model for simulation of analog circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(10): 1193-1207 (1995) - Kamal Chaudhary, Massoud Pedram:
Computing the area versus delay trade-off curves in technology mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(12): 1480-1489 (1995) - Chun-Jung Chen, Wu-Shiung Feng:
Relaxation-based transient sensitivity computations for MOSFET circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2): 173-185 (1995) - C. Y. Roger Chen, Cliff Yungchin Hou, Bradley S. Carlson:
A preprocessor for improving channel routing hierarchical pin permutation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(7): 896-903 (1995) - Ching-Dong Chen, Yuh-Sheng Lee, Allen C.-H. Wu, Youn-Long Lin:
TRACER-fpga: a router for RAM-based FPGA's. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3): 371-374 (1995) - Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin:
Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1076-1084 (1995) - Julie Chen, Andrew T. Yang:
STYLE: a statistical design approach based on nonparametric performance macromodeling. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(7): 794-802 (1995) - C. Y. Roger Chen, Cliff Yungchin Hou:
A pin permutation algorithm for improving over-the-cell channel routing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(8): 1030-1037 (1995) - Eli Chiprout, Michel S. Nakhla:
Analysis of interconnect networks using complex frequency hopping (CFH). IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(2): 186-200 (1995) - Seonghun Cho, Sartaj Sahni:
Minimum area joining of compacted cells. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(7): 903-909 (1995) - Nan-Chi Chou, Lung-Tien Liu, Chung-Kuan Cheng, Wei-Jin Dai, Rodney Lindelof:
Local ratio cut and set covering partitioning for huge logic emulation systems. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(9): 1085-1092 (1995) - Umakanta Choudhury, Alberto L. Sangiovanni-Vincentelli:
Automatic generation of analytical models for interconnect capacitances. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(4): 470-480 (1995) - Weitong Chuang, Sachin S. Sapatnekar, Ibrahim N. Hajj:
Timing and area optimization for standard-cell VLSI circuit design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3): 308-320 (1995) - Moon-Jung Chung, Sangchul Kim:
A path-oriented algorithm for the cell selection problem. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3): 296-307 (1995) - Jason Cong, Kwok-Shing Leung:
Optimal wiresizing under Elmore delay model. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 14(3): 321-336 (1995)
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