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Publication search results
found 24 matches
- 1996
- Abdessatar Abderrahman, Bozena Kaminska, Eduard Cerny:
Optimization-based multifrequency test generation for analog circuits. J. Electron. Test. 9(1-2): 59-73 (1996) - Vishwani D. Agrawal:
Editorial. J. Electron. Test. 9(1-2): 5 (1996) - Javier Argüelles, Salvador Bracho:
Signature analysis for fault detection of mixed-signal ICs based on dynamic power-supply current. J. Electron. Test. 9(1-2): 89-107 (1996) - Ashok Balivada, Hong Zheng, Naveena Nagi, Abhijit Chatterjee, Jacob A. Abraham:
A unified approach for fault simulation of linear mixed-signal circuits. J. Electron. Test. 9(1-2): 29-41 (1996) - Savita Banerjee, Rabindra K. Roy, Srimat T. Chakradhar:
Initialization issues in asynchronous circuit synthesis. J. Electron. Test. 9(3): 237-250 (1996) - Adel Belhaouane, Yvon Savaria, Bozena Kaminska, Daniel Massicotte:
Reconstruction method for jitter tolerant data acquisition system. J. Electron. Test. 9(1-2): 177-185 (1996) - Christian Dufaza, Hassan Ihs:
A BIST-DFT technique for DC test of analog modules. J. Electron. Test. 9(1-2): 117-133 (1996) - Aigars Gertners, Valery Zagursky, Dzintra Saldava:
Behavior model of mixed ADC systems. J. Electron. Test. 9(1-2): 19-27 (1996) - Bozena Kaminska, Bernard Courtois:
Guest editorial. J. Electron. Test. 9(1-2): 7-8 (1996) - Mark G. Karpovsky, Vyacheslav N. Yarmolik:
Transparent random access memory testing for pattern sensitive faults. J. Electron. Test. 9(3): 251-266 (1996) - Chen-Pin Kung, Chen-Shang Lin:
Parallel sequence fault simulation for synchronous sequential circuits. J. Electron. Test. 9(3): 267-277 (1996) - Shyue-Kung Lu, Cheng-Wen Wu
, Ruei-Zong Hwang:
Cell delay fault testing for iterative logic arrays. J. Electron. Test. 9(3): 311-316 (1996) - Andrzej Materka
, Michal Strzelecki
:
Parametric testing of mixed-signal circuits by ANN processing of transient responses. J. Electron. Test. 9(1-2): 187-202 (1996) - Salvador Mir, Marcelo Lubaszewski, Bernard Courtois:
Fault-based ATPG for linear analog circuits with minimal size multifrequency test sets. J. Electron. Test. 9(1-2): 43-57 (1996) - Salvador Mir, Marcelo Lubaszewski, Bernard Courtois:
Unified built-in self-test for fully differential analog circuits. J. Electron. Test. 9(1-2): 135-151 (1996) - Firas Mohamed, Meryem Marzouki:
Test and diagnosis of analog circuits: When fuzziness can lead to accuracy. J. Electron. Test. 9(1-2): 203-216 (1996) - Chen-Yang Pan, Kwang-Ting Cheng
, Sandeep Gupta:
Fault macromodeling and a testing strategy for opamps. J. Electron. Test. 9(3): 225-235 (1996) - D. A. Pierce, Parag K. Lala:
Modular implementation of efficient self-checking checkers for the Berger code. J. Electron. Test. 9(3): 279-294 (1996) - J. Raczkowycz, S. Allott, T. I. Pritchard:
A data optimization test technique for characterizing embedded ADCs. J. Electron. Test. 9(1-2): 165-175 (1996) - Josep Rius, Joan Figueras:
Dynamic characterization of Built-In Current Sensors based on PN junctions: Analysis and experiments. J. Electron. Test. 9(3): 295-310 (1996) - José Machado da Silva, José Silva Matos, Ian M. Bell, Gaynor E. Taylor:
Mixed current/voltage observation towards effective testing of analog and mixed-signal circuits. J. Electron. Test. 9(1-2): 75-88 (1996) - J. van Spaandonk, Tom A. M. Kevenaar:
Selecting measurements to test the functional behavior of analog circuits. J. Electron. Test. 9(1-2): 9-18 (1996) - Johan Verfaillie, Didier Haspeslagh:
A general purpose design-for-test methodology at the analog-digital boundary of mixed-signal VLSI. J. Electron. Test. 9(1-2): 109-115 (1996) - Yingquan Zhou, Mike W. T. Wong, Yinghua Min:
Hardware reduction in continuous checksum-based analog checkers: Algorithm and its analysis. J. Electron. Test. 9(1-2): 153-163 (1996)
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retrieved on 2024-07-18 14:06 CEST from data curated by the dblp team
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