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Publication search results
found 121 matches
- 1989
- Richard Absher, J. E. (Ned) Lecky:
Engineering Curricula for "Meeting the Tests of Time". ITC 1989: 242-244 - Prathima Agrawal, Vishwani D. Agrawal, Kwang-Ting Cheng, Raffi Tutundjian:
Fault Simulation in a Pipelined Multiprocessor System. ITC 1989: 727-734 - Sheldon B. Akers, Winston Jansz:
Test Set Embedding in a Built-In Self-Test Environment. ITC 1989: 257-263 - Kohei Akiyama, Hiroshi Nishimura, Kyoji Anazawa, Akito Kishida, Nobuyuki Kasuga:
High-Resolution Analog Measurement on Mixed-Signal LSI Tester. ITC 1989: 124-128 - Sami A. Al-Arian:
Design and Test in the Universities. ITC 1989: 245-245 - Barry A. Alcorn:
Writing Correct and Usable Specifications for Board Test: A Case Study. ITC 1989: 773-786 - Don Allingham, Pat Bashford, Mike Peters, Dean Vendl:
DesignTestTM: A Solution to the Problems of ASIC Verification. ITC 1989: 893-902 - P. N. Anirudhan, Premachandran R. Menon:
Symbolic Test Generation for Hierarchically Modeled Digital Systems. ITC 1989: 461-469 - W. David Ballew, Lauren M. Streb:
Board-Level Boundary-Scan: Regaining Observability with an Additional IC. ITC 1989: 182-189 - Paul H. Bardell:
Calculating the Effects of Linear Dependencies in m-Sequences Used as Test Stimuli. ITC 1989: 252-256 - Steve Barton:
Characterization of High-Speed (Above 50 MHz) Devices Using Advance ATE-Techniques, Results and Device Problems. ITC 1989: 860-868 - Robert W. Bassett, Barry J. Butkus, Stephen L. Dingle, Marc R. Faucher, Pamela S. Gillis, Jeannie H. Panner, John G. Petrovick, Donald L. Wheater:
Low Cost Testing of High Density Logic Components. ITC 1989: 550-557 - Frans P. M. Beenker, Rob Dekker, Rudi Stans, Max van der Star:
A Testability Strategy for Silicon Compilers. ITC 1989: 660-669 - Moshe Ben-Bassat, Defna Ben-Arie, Israel Beniaminy, Jonathan Cheifetz, Michael Klinger:
A Proposed Benchmark Unit for Evaluating Electronic Troubleshooting Expert Systems. ITC 1989: 78-86 - Jacques Benkoski, Andrzej J. Strojwas:
Computation of Delay Defect and Delay Fault Probabilities Using a Statistical Timing Simulator. ITC 1989: 153-160 - J. R. Birchak, H. K. Haill:
Coupling Coefficients for Signal Lines Separated by Ground Lines on PC Boards. ITC 1989: 190-198 - Donald W. Bouldin:
The Push for Test in Universities. ITC 1989: 246-246 - Daniel Brand, Vijay S. Iyengar:
Synthesis of Pseudo-Random Pattern Testable Designs. ITC 1989: 501-508 - Christopher W. Branson:
A High Performance, 10-Volt Integrated Pin Electronics Driver. ITC 1989: 846-853 - Franc Brglez, Gershon Kedem, Clay Gloster:
Hardware-Based Weighted Random Pattern Generation for Boundary Scan. ITC 1989: 264-274 - Stephen W. Bryson:
Custom Pin Electronics for VLSI Automatic Test Equipment. ITC 1989: 854-859 - John D. Calhoun, Franc Brglez:
A Framework and Method for Hierarchical Test Generation. ITC 1989: 480-490 - F. Camerik, P. A. J. Dirks, Jochen A. G. Jess:
Qualification and Quantification of Process-Induced Product-Related Defects. ITC 1989: 643-652 - Sreejit Chakravarty:
A Testable Realization of CMOS Combinational Circuits. ITC 1989: 509-518 - John C. Chan, Baxter F. Womack:
Diagnostics Based on Fault Signature. ITC 1989: 935 - C. H. Chen, Premachandran R. Menon:
An Approach to Functional Level Testability Analysis. ITC 1989: 373-380 - Kenneth R. Chin:
Functional Testing of Circuits and SMD Boards with Limited Nodal Access. ITC 1989: 129-143 - C. C. Chuang, Anup K. Gupta:
The Analysis of Parallel BIST by the Combined Markov Chain (CMC) Model. ITC 1989: 337-343 - Anton T. Dahbura, M. Ümit Uyar, Chi W. Yau:
An Optimal Test Sequence for the JTAG/IEEE P1149.1 Test Access Port Controller. ITC 1989: 55-62 - Wayne D. Dettloff, Melodie D. Tebbs:
The Omnitest System: A No-Generate, No-Compile, Interactive Test Methodology. ITC 1989: 572-576
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