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Publication search results
found 141 matches
- 1997
- Marleen Adé, Rudy Lauwereins, J. A. Peperstraete:
Data Memory Minimisation for Synchronous Data Flow Graphs Emulated on DSP-FPGA Targets. DAC 1997: 64-69 - Samir Agrawal, Rajesh K. Gupta:
Data-Flow Assisted Behavioral Partitioning for Embedded Systems. DAC 1997: 709-712 - Charles J. Alpert, Tony F. Chan, Dennis J.-H. Huang, Igor L. Markov, Kenneth Yan:
Quadratic Placement Revisited. DAC 1997: 752-757 - Charles J. Alpert, Anirudh Devgan:
Wire Segmenting for Improved Buffer Insertion. DAC 1997: 588-593 - Charles J. Alpert, Jen-Hsin Huang, Andrew B. Kahng:
Multilevel Circuit Partitioning. DAC 1997: 530-533 - Narayan R. Aluru, James White:
Algorithms for Coupled Domain MEMS Simulation. DAC 1997: 686-690 - Tod Amon, Gaetano Borriello, Taokuan Hu, Jiwen Liu:
Symbolic Timing Verification of Timing Diagrams using Presburger Formulas. DAC 1997: 226-231 - Smita Bakshi, Daniel Gajski:
Hardware/Software Partitioning and Pipelining. DAC 1997: 713-716 - Felice Balarin, Alberto L. Sangiovanni-Vincentelli:
Schedule Validation for Embedded Reactive Real-Time Systems. DAC 1997: 52-57 - Donald G. Baltus, Thomas Varga, Robert C. Armstrong, John Duh, T. G. Matheson:
Developing a Concurrent Methodology for Standard-Cell Library Generation. DAC 1997: 333-336 - Matthias Bauer, Wolfgang Ecker:
Hardware/Software Co-Simulation in a VHDL-Based Test Bench Approach. DAC 1997: 774-779 - Michael W. Beattie, Lawrence T. Pileggi:
Bounds for BEM Capacitance Extraction. DAC 1997: 133-136 - Luca Benini, Enrico Macii, Massimo Poncino:
Telescopic Units: Increasing the Average Throughput of Pipelined Designs by Adaptive Latency Control. DAC 1997: 22-27 - Ole Bentz, Jan M. Rabaey, David Lidsky:
A Dynamic Design Estimation and Exploration Environment. DAC 1997: 190-195 - Robert W. Brodersen:
InfoPad - An Experiment in System Level Design and Integration. DAC 1997: 313-314 - Gianpiero Cabodi, Paolo Camurati, Luciano Lavagno, Stefano Quer:
Disjunctive Partitioning and Partial Iterative Squaring: An Effective Approach for Symbolic Traversal of Large Circuits. DAC 1997: 728-733 - Chin-Chih Chang, Jason Cong:
An Efficient Approach to Multi-Layer Layer Assignment with Application to Via Minimization. DAC 1997: 600-603 - Douglas Chang, Mike Tien-Chien Lee, Malgorzata Marek-Sadowska, Takashi Aikyo, Kwang-Ting Cheng:
A Test Synthesis Approach to Reducing BALLAST DFT Overhead. DAC 1997: 466-471 - Chau-Shen Chen, TingTing Hwang, C. L. Liu:
Low Power FPGA Design - A Re-engineering Approach. DAC 1997: 656-661 - Howard H. Chen, David D. Ling:
Power Supply Noise Analysis Methodology for Deep-Submicron VLSI Chip Design. DAC 1997: 638-643 - Chung-Ping Chen, D. F. Wong:
Optimal Wire-Sizing Function with Fringing Capacitance Consideration. DAC 1997: 604-607 - Jason Cong, Lei He, Andrew B. Kahng, David Noice, Nagesh Shirali, Steve H.-C. Yen:
Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology. DAC 1997: 627-632 - Jason Cong, Chang Wu:
FPGA Synthesis with Retiming and Pipelining for Clock Period Minimization of Sequential Circuits. DAC 1997: 644-649 - Donald R. Cottrell:
Electronic Component Information Exchange (ECIX). DAC 1997: 559-563 - Olivier Coudert:
Exact Coloring of Real-Life Graphs is Easy. DAC 1997: 121-126 - John F. Croix, D. F. Wong:
A Fast And Accurate Technique To Optimize Characterization Tables For Logic Synthesis. DAC 1997: 337-340 - Ajay J. Daga, Peter Suaris:
Interface Timing Verification Drives System Design. DAC 1997: 240-245 - Wayne Wei-Ming Dai:
Chip Parasitic Extraction and Signal Integrity Verification (Extended Abstract). DAC 1997: 717-719 - Florentin Dartu, Lawrence T. Pileggi:
Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling. DAC 1997: 46-51 - Bharat P. Dave, Ganesh Lakshminarayana, Niraj K. Jha:
COSYN: Hardware-Software Co-Synthesis of Embedded Systems. DAC 1997: 703-708
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