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Publication search results
found 116 matches
- 2024
- Sourav Roy, Subhadeep Paul, Tapas Kumar Maiti:
VLSI Architectures of Forward Kinematic Processor for Robotics Applications. CoRR abs/2403.04537 (2024) - 2023
- Shih-Chang Hsia, Szu-Hong Wang, Ting-Tseng Kuo:
VLSI architecture and implementation of HDR camera signal processor. J. Real Time Image Process. 20(1): 6 (2023) - 2022
- Pai-Yu Tan, Chih-Hsuan Tung, Cheng-Wen Wu, Mincent Lee, Gordon Liao:
A Memory Built-In Peer-Repair Architecture for Mesh-Connected Processor Array. VLSI-DAT 2022: 1-4 - 2021
- Yu-Sheng Lin, Wei-Chao Chen, Trista Pei-Chun Chen:
Tensor-Centric Processor Architecture for Applications in Advanced Driver Assistance Systems. VLSI-DAT 2021: 1-3 - Steven Colleman, Thomas Verelst, Linyan Mei, Tinne Tuytelaars, Marian Verhelst:
Processor Architecture Optimization for Spatially Dynamic Neural Networks. VLSI-SoC 2021: 1-6 - Juhyoung Lee, Jihoon Kim, Wooyoung Jo, Sangyeob Kim, Sangjin Kim, Jinsu Lee, Hoi-Jun Yoo:
A 13.7 TFLOPS/W Floating-point DNN Processor using Heterogeneous Computing Architecture with Exponent-Computing-in-Memory. VLSI Circuits 2021: 1-2 - 2020
- Wei-Jhe Chen, Yu-An Lai, Chung-An Shen:
The VLSI Architecture and Implementation of a Low Complexity and Highly Efficient Configurable SVD Processor for MIMO Communication Systems. Circuits Syst. Signal Process. 39(12): 6231-6246 (2020) - Segi Lee, Sugil Lee, Jongeun Lee, Jong-Moon Choi, Do-Wan Kwon, Seung-Kwang Hong, Kee-Won Kwon:
Architecture-Accuracy Co-optimization of ReRAM-based Low-cost Neural Network Processor. ACM Great Lakes Symposium on VLSI 2020: 427-432 - 2019
- Anirban Chakraborty, Ayan Banerjee:
Modular and parallel VLSI architecture of multi-dimensional quad-core GA co-processor for real time image/video processing. Microprocess. Microsystems 65: 180-195 (2019) - Donghyeon Han, Jinsu Lee, Jinmook Lee, Hoi-Jun Yoo:
A 1.32 TOPS/W Energy Efficient Deep Neural Network Learning Processor with Direct Feedback Alignment based Heterogeneous Core Architecture. VLSI Circuits 2019: 304- - 2017
- Tzu-Ting Tseng, Chung-An Shen:
The VLSI architecture of a highly efficient configurable pre-processor for MIMO detections. IPCCC 2017: 1-5 - 2016
- Anastasios Psarras, Junghee Lee, Pavlos M. Mattheakis, Chrysostomos Nicopoulos, Giorgos Dimitrakopoulos:
A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors. ACM Great Lakes Symposium on VLSI 2016: 335-340 - Gopinath Mahale, Soumitra Kumar Nandy, Eshan Bhatia, S. K. Nandy, Ranjani Narayan:
VOP: Architecture of a Processor for Vector Operations in On-Line Learning of Neural Networks. VLSID 2016: 391-396 - 2015
- Neethu Bal Mallya, Geeta Patil, Biju K. Raveendran:
Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors. VLSID 2015: 65-70 - 2014
- Masaki Nakanishi, Miki Matsuyama, Yumi Yokoo:
A quantum algorithm processor architecture based on register reordering. VLSI-SoC 2014: 1-6 - 2013
- Sajad A. Loan, Asim M. Murshid, Shuja A. Abbasi, Abdul Rahman M. Alamoud:
A novel VLSI architecture for a fuzzy inference processor using Gaussian-shaped membership function. J. Intell. Fuzzy Syst. 24(1): 5-19 (2013) - Vassilios A. Chouliaras, Konstantia Koutsomyti, Simon Parr, David J. Mulvaney, Mark Milward:
Architecture, performance modeling and VLSI implementation methodologies for ASIC vector processors: A case study in telephony workloads. Microprocess. Microsystems 37(8-D): 1122-1143 (2013) - Takahiro Hanyu:
Challenge of MTJ/MOS-hybrid logic-in-memory architecture for nonvolatile VLSI processor. ISCAS 2013: 117-120 - Kuan-Ju Huang, Jui-Chung Chang, Chih-Wei Feng, Wai-Chi Fang:
A parallel VLSI architecture of singular value decomposition processor for real-time multi-channel EEG system. ISCE 2013: 21-22 - 2012
- Asim M. Murshid, S. N. Ahmad:
VLSI Architecture for Fuzzy Inference Processor using Triangular-Shaped Membership Function. Comput. Inf. Sci. 5(1): 113-122 (2012) - Osman Allam, Stijn Eyerman, Lieven Eeckhout:
An efficient CPI stack counter architecture for superscalar processors. ACM Great Lakes Symposium on VLSI 2012: 55-58 - Hamed Tabkhi, Gunar Schirner:
ARRA: Application-guided reliability-enhanced registerfile architecture for embedded processors. VLSI-SoC 2012: 299-302 - Zhibin Xiao, Bevan M. Baas:
A hexagonal shaped processor and interconnect topology for tightly-tiled many-core architecture. VLSI-SoC 2012: 153-158 - Zhibin Xiao, Bevan M. Baas:
A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks. VLSI-SoC (Selected Papers) 2012: 125-143 - 2011
- Alexey Lopich, Piotr Dudek:
Architecture and design of a programmable 3D-integrated cellular processor array for image processing. VLSI-SoC 2011: 349-353 - 2010
- Andy Motten, Luc Claesen:
A binary adaptable window SoC architecture for a stereo vision based depth field processor. VLSI-SoC 2010: 25-30 - Yuan Xie:
Processor Architecture Design Using 3D Integration Technology. VLSI Design 2010: 446-451 - 2008
- Andre Guntoro, Hans-Peter Keil, Manfred Glesner:
High-Speed Configurable VLSI Architecture of a General Purpose Lifting-Based Discrete Wavelet Processor. ICETE (Selected Papers) 2008: 318-330 - Kiwon Yoo, Jae Hun Lee, Kwanghoon Sohn:
VLSI architecture design of motion vector processor for H.264/AVC. ICIP 2008: 1412-1415 - Andre Guntoro, Hans-Peter Keil, Manfred Glesner:
Configurable VLSI Architecture of a General Purpose Lifting-based Wavelet Processor. SIGMAP 2008: 69-75
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