"A Hexagonal Processor and Interconnect Topology for Many-Core Architecture ..."

Zhibin Xiao, Bevan M. Baas (2012)

> Home

Details and statistics

DOI: 10.1007/978-3-642-45073-0_7

access: open

type: Conference or Workshop Paper

metadata version: 2018-06-26

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - conf/vlsi/XiaoB12a
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsi/XiaoB12a
Zhibin Xiao, Bevan M. Baas:
A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks. VLSI-SoC (Selected Papers) 2012: 125-143

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.