- Suvadeep Banerjee, Steve Burns, Pasquale Cocchini, Abhijit Davare, Shweta Jain, Desmond Kirkpatrick, Anton Sorokin, Jin Yang, Zhenkun Yang:
A Highly Configurable Hardware/Software Stack for DNN Inference Acceleration. CoRR abs/2111.15024 (2021) - Kemal Derya, Ahmet Can Mert, Erdinç Öztürk, Erkay Savas:
CoHA-NTT: A Configurable Hardware Accelerator for NTT-based Polynomial Multiplication. IACR Cryptol. ePrint Arch. 2021: 1527 (2021) - Afifa Ishtiaq, Muhammad Shafique, Osman Hassan:
CARiMoL: A Configurable Hardware Accelerator for Ringand Module Lattice-Based Post-Quantum Cryptography. IACR Cryptol. ePrint Arch. 2021: 714 (2021) - Arpan Jati, Naina Gupta, Anupam Chattopadhyay, Somitra Kumar Sanadhya:
A Configurable Crystals-Kyber Hardware Implementation with Side-Channel Protection. IACR Cryptol. ePrint Arch. 2021: 1189 (2021) - Jan Philipp Thoma, Tim Güneysu:
A Configurable Hardware Implementation of XMSS. IACR Cryptol. ePrint Arch. 2021: 352 (2021) - 2020
- Yibo Fan, Leilei Huang, Kewei Chen, Xiaoyang Zeng:
A Highly Configurable 7.62GOP/s Hardware Implementation for LSTM. IEICE Trans. Electron. 103-C(5): 263-273 (2020) - Roger Endrigo Carvalho Porto, Marcel Moscarelli Corrêa, Jones Goebel, Bruno Zatt, Nuno Roma, Luciano Agostini, Marcelo Schiavon Porto:
UHD 8K energy-quality scalable HEVC intra-prediction SAD unit hardware using optimized and configurable imprecise adders. J. Real Time Image Process. 17(5): 1685-1701 (2020) - Ahmet Can Mert, Erdinç Öztürk, Erkay Savas:
FPGA implementation of a run-time configurable NTT-based polynomial multiplication hardware. Microprocess. Microsystems 78: 103219 (2020) - Vinay Chamola, Sambit Patra, Neeraj Kumar, Mohsen Guizani:
FPGA for 5G: Re-configurable Hardware for Next Generation Communication. IEEE Wirel. Commun. 27(3): 140-147 (2020) - Tanfer Alan, Andreas Gerstlauer, Jörg Henkel:
Runtime Accuracy-Configurable Approximate Hardware Synthesis Using Logic Gating and Relaxation. DATE 2020: 1578-1581 - Samuel Dewan, Paulo Garcia:
Programming Abstractions for Configurable Hardware: Survey and Research Directions. FPGA 2020: 310 - Venkata Krishnan, Olivier Serres, Michael Blocksome:
COnfigurable Network Protocol Accelerator (COPA) † : An Integrated Networking/Accelerator Hardware/Software Framework. Hot Interconnects 2020: 17-24 - William Butera:
A Dynamically Configurable Network for Software-Defined Hardware. HPEC 2020: 1-7 - Kasem Khalil, Bappaditya Dey, Yasser Sherazi, Ashok Kumar, Magdy A. Bayoumi:
A Novel Design Reversible Logic Based Configurable Fault-Tolerant Embryonic Hardware. ISCAS 2020: 1-5 - Xiao Hu, Zhonghai Lu:
A Configurable Hardware Architecture for Runtime Application of Network Calculus. NPC 2020: 203-216 - Alessandro Veronesi, Milos Krstic, Davide Bertozzi:
Cross-Layer Hardware/Software Assessment of the Open-Source NVDLA Configurable Deep Learning Accelerator. VLSI-SOC 2020: 58-63 - 2019
- Pietro Nannipieri, Gianmarco Dinelli, Luca Fanucci:
A Configurable Hardware Word Re-Ordering Block for Multi-Lane Communication Protocols: Design and Use Case. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 102-A(5): 747-749 (2019) - Indar Sugiarto, Cristian Axenie, Jörg Conradt:
FPGA-Based Hardware Accelerator for an Embedded Factor Graph with Configurable Optimization. J. Circuits Syst. Comput. 28(2): 1950031:1-1950031:30 (2019) - Jiahao Lu, Xianghua Luo, Dongsheng Liu, Peng Liu, Bo Liu:
A Configurable Architecture of ANN in Hardware with Resource-Efficient Reusable Neuron. ASICON 2019: 1-4 - Jo Vliegen, Md Masoom Rabbani, Mauro Conti, Nele Mentens:
SACHa: Self-Attestation of Configurable Hardware. DATE 2019: 746-751 - Oana Boncalo, Alexandru Amaricai, Zsófia Lendek:
Configurable Hardware Accelerator Architecture for a Takagi-Sugeno Fuzzy Controller. DSD 2019: 96-101 - Ghada Dessouky, Shaza Zeitouni, Ahmad Ibrahim, Lucas Davi, Ahmad-Reza Sadeghi:
CHASE: A Configurable Hardware-Assisted Security Extension for Real-Time Systems. ICCAD 2019: 1-8 - Praveen Kumar, Aishwarya Mittal, Kakarla Uday Kanth Reddy, Shubham Chowdhary, Vishal Kumar, Rajendra Pratap:
Design and Verification of Three Phase Sequence Decomposer on Re-configurable Hardware. ICCCNT 2019: 1-5 - Steinar Thune Christensen, Snorre Aunet, Omer Qadir:
A Configurable and Versatile Architecture for Low Power, Energy Efficient Hardware Acceleration of Convolutional Neural Networks. NORCAS 2019: 1-6 - Menbere Kina Tekleyohannes, Vladimir Rybalkin, Muhammad Mohsin Ghaffar, Norbert Wehn, Andreas Dengel:
iDocChip - A Configurable Hardware Architecture for Historical Document Image Processing: Text Line Extraction. ReConFig 2019: 1-8 - Jo Vliegen, Md Masoom Rabbani, Mauro Conti, Nele Mentens:
A Novel FPGA Architecture and Protocol for the Self-attestation of Configurable Hardware. IACR Cryptol. ePrint Arch. 2019: 405 (2019) - 2018
- Lekhobola Tsoeunyane, Simon Winberg, Michael Inggs:
Automatic Configurable Hardware Code Generation for Software-Defined Radios. Comput. 7(4): 53 (2018) - Baluprithviraj Krishnaswamy Natarajan, Vijayachitra Senniappan:
Logic obfuscation technique using configurable gate diffusion input for improved hardware security. IEICE Electron. Express 15(19): 20180802 (2018) - Teng-Wei Chu, Chung-An Shen, Chun-Wei Wu:
The hardware and software co-design of a configurable QoS for video streaming based on OpenFlow protocol and NetFPGA platform. Multim. Tools Appl. 77(7): 9071-9091 (2018) - Vladimir Rybalkin, Syed Saqib Bukhari, Muhammad Mohsin Ghaffar, Aqib Ghafoor, Norbert Wehn, Andreas Dengel:
iDocChip: A Configurable Hardware Architecture for Historical Document Image Processing: Percentile Based Binarization. DocEng 2018: 24:1-24:8