- Alex G. Dickinson, John S. Denker:
Adiabatic dynamic logic. IEEE J. Solid State Circuits 30(3): 311-315 (1995) - Ivo Dobbelaere, Mark Horowitz, Abbas El Gamal:
Regenerative feedback repeaters for programmable interconnections. IEEE J. Solid State Circuits 30(11): 1246-1253 (1995) - Steven M. Domer, Samuel A. Foertsch, Glenn D. Raskin:
Model for yield and manufacturing prediction on VLSI designs for advanced technologies, mixed circuitry, and memories. IEEE J. Solid State Circuits 30(3): 286-294 (1995) - Rob van Dongen, Vincent Rikkink:
A 1.5 V class AB CMOS buffer amplifier for driving low-resistance loads. IEEE J. Solid State Circuits 30(12): 1333-1338 (1995) - Jim Dunning, Gerald Garcia, Jim Lundberg, Ed Nuckolls:
An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors. IEEE J. Solid State Circuits 30(4): 412-422 (1995) - J. Francisco Duque-Carrillo
, Raquel Pérez-Aloe, José M. Valverde:
Biasing circuit for high input swing operational amplifiers. IEEE J. Solid State Circuits 30(2): 156-159 (1995) - Santanu Dutta, Shivaling S. Mahant-Shetti, Stephen L. Lusky:
A comprehensive delay model for CMOS inverters. IEEE J. Solid State Circuits 30(8): 864-871 (1995) - Toshiaki Eirihata, Sang H. Dhong, Lewis M. Terman, Toshio Sunaga, Yoischi Taira:
A variable precharge voltage sensing. IEEE J. Solid State Circuits 30(1): 25-28 (1995) - Sherif H. K. Embabi, Abdellatif Bellaouar, Kazi Islam:
A bootstrapped bipolar CMOS (B2CMOS) Gate for low-voltage applications. IEEE J. Solid State Circuits 30(1): 47-53 (1995) - Robert J. Evans, Paul D. Franzon
:
Energy consumption modeling and optimization for SRAM's. IEEE J. Solid State Circuits 30(5): 571-579 (1995) - Ivars G. Finvers, James W. Haslett, Fred N. Trofimenkoff:
A high temperature precision amplifier. IEEE J. Solid State Circuits 30(2): 120-128 (1995) - Navid Foroudi, Tadeusz Kwasniewski:
CMOS high-speed dual-modulus frequency divider for RF frequency synthesis. IEEE J. Solid State Circuits 30(2): 93-100 (1995) - Steven L. Garverick, Lany Skrenes, Richard D. Baertsch:
A 32-channel charge readout IC for programmable, nonlinear quantization of multichannel detector data. IEEE J. Solid State Circuits 30(5): 533-541 (1995) - Benjamin M. Gordon, Teresa H. Meng:
A 1.2 mW video-rate 2-D color subband decoder. IEEE J. Solid State Circuits 30(12): 1510-1516 (1995) - Richard X. Gu, Mohamed I. Elmasry:
Novel high speed circuit structures for BiCMOS environment. IEEE J. Solid State Circuits 30(5): 563-570 (1995) - Jerry Hallmark, Carl Shurboff, Bill Ooms, Rudy Lucero, Jon Abrokwah, Jenn-Hwa Huang:
0.9-V DSP blocks: a 15-ns 4-k SRAM and a 45-ns 16-b multiply/accumulator. IEEE J. Solid State Circuits 30(10): 1136-1140 (1995) - Takahiro Hanyu, Michitaka Kameyama:
A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic. IEEE J. Solid State Circuits 30(11): 1239-1245 (1995) - Yutaka Harada:
Delay components of a current mode logic circuit and their current dependency. IEEE J. Solid State Circuits 30(1): 54-60 (1995) - Robert A. Hawley, Thu-ji Lin, Henry Samueli:
A 300 MHz digital double-sideband to single-sideband converter in 1 μm CMOS. IEEE J. Solid State Circuits 30(1): 4-10 (1995) - Frederick P. Herrmann, Charles G. Sodini:
A 256-element associative parallel processor. IEEE J. Solid State Circuits 30(4): 365-370 (1995) - Shigeki Hino, Minoru Togashi, Kimiyoshi Yamasaki:
Asynchronous transfer mode switching LSI chips with 10-Gb/s serial I/O ports. IEEE J. Solid State Circuits 30(4): 348-352 (1995) - Mitsuru Hiraki, Hirotsugu Kojima, Hitoshi Misawa, Takashi Akazawa, Yuji Hatano:
Data-dependent logic swing internal bus architecture for ultralow-power LSI's. IEEE J. Solid State Circuits 30(4): 397-402 (1995) - Richard F. Hobson, Michael W. Fraser:
An efficient maximum-redundancy radix-8 SRT division and square-root method. IEEE J. Solid State Circuits 30(1): 29-38 (1995) - Fleming Hoeg, Stephen I. Long, Uddalak Bhattacharya:
Design and performance of multistage GaAs dynamic logic. IEEE J. Solid State Circuits 30(5): 580-585 (1995) - W. Timothy Holman, J. Alvin Connelly:
A compact low noise operational amplifier for a 1.2 μm digital CMOS technology. IEEE J. Solid State Circuits 30(6): 710-714 (1995) - Paul J. Hurst, Bret C. Rothenberg:
A programmable clock generator that uses noise shaping and its application in switched-capacitor filters. IEEE J. Solid State Circuits 30(4): 403-411 (1995) - Kazunari Inoue, Hisashi Nakamura, Hiroyuki Kawai:
A 10 Mb frame buffer memory with Z-compare and A-blend units. IEEE J. Solid State Circuits 30(12): 1563-1568 (1995) - Koichiro Ishibashi, Kunihiro Komiyaji, Hiroshi Toyoshima, Masataka Minami, Nagatoshi Ohki, Hiroshi Ishida, Toshiaki Yamanaka, Takahiro Nagano, Takashi Nishida:
A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL. IEEE J. Solid State Circuits 30(11): 1189-1195 (1995) - Koichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida:
A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers. IEEE J. Solid State Circuits 30(4): 480-486 (1995) - Noboru Ishihara, Shuichi Fujita, Minoru Togashi, Shigeki Hino, Yoshimitsu Arai, Nobuyuki Tanaka, Yoshiji Kobayashi, Yukio Akazawa:
3.5-Gb/s⨉4-ch Si bipolar LSI's for optical interconnections. IEEE J. Solid State Circuits 30(12): 1493-1501 (1995)