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ORCID"A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL."
Koichiro Ishibashi et al. (1995)
- Koichiro Ishibashi, Kunihiro Komiyaji, Hiroshi Toyoshima, Masataka Minami, Nagatoshi Ohki, Hiroshi Ishida, Toshiaki Yamanaka, Takahiro Nagano, Takashi Nishida:
A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL. IEEE J. Solid State Circuits 30(11): 1189-1195 (1995)
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