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ORCIDTakashi Nishida
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2010 – 2019
- 2010
[j13]Li Lu, Masahiro Echizen, Takashi Nishida, Kiyoshi Uchiyama, Yukiharu Uraoka:
Electrical Properties of Ba0.5Sr0.5Ta2O6 Thin Film Fabricated by Sol-Gel Method. IEICE Trans. Electron. 93-C(10): 1511-1515 (2010)
1990 – 1999
- 1995
- [j12]Koichiro Ishibashi, Koichi Takasugi, Kunihiro Komiyaji, Hiroshi Toyoshima, Toshiaki Yamanaka, Akira Fukami, Naotaka Hashimoto, Nagatoshi Ohki, Akihiro Shimizu, Takashi Hashimoto, Takahiro Nagano, Takashi Nishida:
A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers. IEEE J. Solid State Circuits 30(4): 480-486 (1995) - [j11]Takeshi Sakata, Masashi Horiguchi, Tomonori Sekiguchi, Shigeki Ueda, Hitoshi Tanaka, Eiji Yamasaki, Yoshinobu Nakagome, Masakazu Aoki, Toru Kaga, Makoto Ohkura, Ryo Nagai, Fumio Murai, Toshihiko Tanaka, Shimpei Iijima, Natsuki Yokoyama, Yasushi Gotoh, Ken'ichi Shoji, Teruaki Kisu, Hisaomi Yamashita, Takashi Nishida, Eiji Takeda:
An experimental 220-MHz 1-Gb DRAM with a distributed-column-control architecture. IEEE J. Solid State Circuits 30(11): 1165-1173 (1995) - [j10]Koichiro Ishibashi, Kunihiro Komiyaji, Hiroshi Toyoshima, Masataka Minami, Nagatoshi Ohki, Hiroshi Ishida, Toshiaki Yamanaka, Takahiro Nagano, Takashi Nishida:
A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL. IEEE J. Solid State Circuits 30(11): 1189-1195 (1995) - 1994
- [c2]Hiroshi Hosoi, Yoshiaki Tsuta, Takashi Nishida, Kiyotaka Murata, Fumihiko Ohta, Tsuyoshi Mekata, Yumiko Kato:
Hearing aid evaluation using variable - speech - rate audiometry. ICSLP 1994: 1995-1998 - 1993
- [j9]Goro Kitsukawa, Masashi Horiguchi, Yoshiki Kawajiri, Takayuki Kawahara
, Takesada Akiba, Yasushi Kawase, Toshikazu Tachibana, Takeshi Sakai, Masakazu Aoki, Syoji Shukuri, Kazuhiko Sagara, Ryo Nagai, Yuzuru Ohji, Nono Hasegawa, Natsuki Yokoyama, Teruaki Kisu, Hisaomi Yamashita, Tokuo Kure, Takashi Nishida:
256-Mb DRAM circuit technologies for file applications. IEEE J. Solid State Circuits 28(11): 1105-1113 (1993) - 1992
- [j8]Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, M. Hanawa, Masato Suzuki, S. Morita, A. Kawamata, Nagatoshi Ohki, Takashi Nishida, Koichi Seki:
3.3-V BiCMOS circuit techniques for 250-MHz RISC arithmetic modules. IEEE J. Solid State Circuits 27(3): 373-381 (1992) - [j7]Mitsuru Hiraki, Kazuo Yano, Masataka Minami, Kazushige Sato, Nozomu Matsuzaki, Atsuo Watanabe, Takashi Nishida, Katsuro Sasaki, Koichi Seki:
A 1.5-V full-swing BiCMOS logic circuit. IEEE J. Solid State Circuits 27(11): 1568-1574 (1992) - 1991
- [j6]Yoshinobu Nakagome, Hitoshi Tanaka, Kan Takeuchi, Eiji Kume, Yasushi Watanabe, Toru Kaga, Yoshifumi Kawamoto, Fumio Murai, Ryuichi Izawa, Digh Hisamoto, Teruaki Kisu, Takashi Nishida, Eiji Takeda, Kiyoo Itoh:
An experimental 1.5-V 64-Mb DRAM. IEEE J. Solid State Circuits 26(4): 465-472 (1991) - [j5]Yoshinobu Nakagome, Kiyoo Itoh, Kan Takeuchi, Eiji Kume, Hitoshi Tanaka, Masanori Isoda, Tatsunori Musha, Toru Kaga, Teruaki Kisu, Takashi Nishida, Yoshifumi Kawamoto, Masakazu Aoki:
Circuit techniques for 1.5-3.6-V battery-operated 64-Mb DRAM. IEEE J. Solid State Circuits 26(7): 1003-1010 (1991) - [j4]Katsutaka Kimura, Takeshi Sakata, Kiyoo Itoh, Toru Kaga, Takashi Nishida, Yoshifumi Kawamoto:
A block-oriented RAM with half-sized DRAM cell and quasi-folded data-line architecture. IEEE J. Solid State Circuits 26(11): 1511-1518 (1991) - [j3]Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Yasuo Onose, Mitsuru Hirao, Nagatoshi Ohki, Takashi Nishida, Koichi Seki, Katsuhiro Shimohigashi:
Quasi-complementary BiCMOS for sub-3-V digital circuits. IEEE J. Solid State Circuits 26(11): 1708-1719 (1991) - [c1]M. Hanawa, Tadahiko Nishimukai, O. Nishii, Masato Suzuki, Kazuo Yano, Mitsuru Hiraki, Shoji Shukuri, Takashi Nishida:
On-Chip Multiple Superscalar Processors with Secondary Cache Memories. ICCD 1991: 128-131 - 1990
- [j2]Kazuo Yano, Toshiaki Yamanaka, Takashi Nishida, Masayoshi Saito, Katsuhiro Shimohigashi, Akihiro Shimizu:
A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic. IEEE J. Solid State Circuits 25(2): 388-395 (1990)
1980 – 1989
- 1989
- [j1]Katsuro Sasaki, Koichiro Ishibashi, Toshiaki Yamanaka, Naotaka Hashimoto, Takashi Nishida, Katsuhiro Shimohigashi, Shoji Hanamura, Shigeru Honjo:
A 9-ns 1-Mbit CMOS SRAM. IEEE J. Solid State Circuits 24(5): 1219-1225 (1989)
Coauthor Index
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