- Ronaldo Husemann, Mariano Majolo, Victor Guimarães, Altamiro Amadeu Susin, Valter Roesler, José Valdeni de Lima:
Hardware integrated quantization solution for improvement of computational H.264 encoder module. VLSI-SoC 2010: 316-321 - Diego Jaccottet, Eduardo Costa, Levent Aksoy, Paulo F. Flores, José Monteiro:
Design of low-complexity and high-speed digital Finite Impulse Response filters. VLSI-SoC 2010: 292-297 - Hailong Jiao, Volkan Kursun:
Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits. VLSI-SoC 2010: 347-351 - Víctor Jiménez, Roberto Gioiosa, Eren Kursun, Francisco J. Cazorla, Chen-Yong Cher, Alper Buyuktosunoglu, Pradip Bose, Mateo Valero:
Trends and techniques for energy efficient architectures. VLSI-SoC 2010: 276-279 - Maher Jridi, Ayman Alfalou:
A low-power, high-speed DCT architecture for image compression: Principle and implementation. VLSI-SoC 2010: 304-309 - Jongpil Jung, Seonpil Kim, Chong-Min Kyung:
Latency-aware Utility-based NUCA Cache Partitioning in 3D-stacked multi-processor systems. VLSI-SoC 2010: 125-130 - Zohreh Karimi, Majid Sarrafzadeh:
Fine-grained post placement voltage assignment considering level shifter overhead. VLSI-SoC 2010: 73-78 - Rafik Khereddine, Louay Abdallah, Emmanuel Simeu, Salvador Mir, Fabio Cenni:
Adaptive logical control of RF LNA performances for efficient energy consumption. VLSI-SoC 2010: 161-166 - Eliyah Kilada, Shomit Das, Kenneth S. Stevens:
Synchronous elasticization: Considerations for correct implementation and MiniMIPS case study. VLSI-SoC 2010: 7-12 - Ji Kong, Peilin Liu:
A novel reconfigurable scratchpad memory for audio applications on cost-effective SoC. VLSI-SoC 2010: 402-407 - Manthena Vamshi Krishna, Juan Xie, Manh Anh Do, Chirn Chye Boon, Kiat Seng Yeo, Aaron V. T. Do:
A 1.8-V 3.6-mW 2.4-GHz fully integrated CMOS frequency synthesizer for IEEE 802.15.4. VLSI-SoC 2010: 387-391 - Seunghan Lee, Kyungsu Kang, Chong-Min Kyung:
Temperature- and bus traffic- aware data placement in 3D-stacked cache. VLSI-SoC 2010: 352-357 - Kuan Jen Lin, Yu Chan Chiu, Tzu-Hao Lin:
A decimal squarer with efficient partial product generation. VLSI-SoC 2010: 213-218 - Ding-Guo Lin, Bing-Hsun Lu, Herming Chiueh:
An 100MHz to 1.6GHz DLL-based clock generator using a feedback-switching detector. VLSI-SoC 2010: 101-104 - Michele Magno, Alessandro Lanza, Davide Brunelli, Luigi Di Stefano, Luca Benini:
Energy aware multimodal embedded video surveillance. VLSI-SoC 2010: 264-269 - Jimson Mathew, Savita Banerjee, Hafizur Rahaman, Dhiraj K. Pradhan, Saraju P. Mohanty, Abusaleh M. Jabir:
On the synthesis of attack tolerant cryptographic hardware. VLSI-SoC 2010: 286-291 - Debora Matos, Miklecio Costa, Luigi Carro, Altamiro Amadeu Susin:
Network interface to synchronize multiple packets on NoC-based Systems-on-Chip. VLSI-SoC 2010: 31-36 - Pramod Kumar Meher:
An optimized lookup-table for the evaluation of sigmoid function for artificial neural networks. VLSI-SoC 2010: 91-95 - Pramod Kumar Meher:
Novel input coding technique for high-precision LUT-based multiplication for DSP applications. VLSI-SoC 2010: 201-206 - Paolo Meloni, Simone Secchi, Luigi Raffo:
Enabling fast Network-on-Chip topology selection: an FPGA-based runtime reconfigurable prototyper. VLSI-SoC 2010: 43-48 - Andy Motten, Luc Claesen:
A binary adaptable window SoC architecture for a stereo vision based depth field processor. VLSI-SoC 2010: 25-30 - Jayram Moorkanikara Nageswaran, Micah Richert, Nikil D. Dutt, Jeffrey L. Krichmar:
Towards reverse engineering the brain: Modeling abstractions and simulation frameworks. VLSI-SoC 2010: 1-6 - Shoichi Nishida, Jyunya Eto, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga, Toshinori Sueyoshi:
Power-aware FPGA routing fabrics and design tools. VLSI-SoC 2010: 67-72 - Preeti Ranjan Panda, Anant Vishnoi, M. Balakrishnan:
Enhancing post-silicon processor debug with Incremental Cache state Dumping. VLSI-SoC 2010: 55-60 - Alessandro Panella, Marco D. Santambrogio, Francesco Redaelli, Fabio Cancare, Donatella Sciuto:
A design workflow for dynamically reconfigurable multi-FPGA systems. VLSI-SoC 2010: 414-419 - Héctor Pettenghi, Ricardo Chaves, Leonel Sousa, Maria J. Avedillo:
An improved RNS generator 2n +/- k based on threshold logic. VLSI-SoC 2010: 119-124 - Roman Plyaskin, Alejandro Masrur, Martin Geier, Samarjit Chakraborty, Andreas Herkersdorf:
High-level timing analysis of concurrent applications on MPSoC platforms using memory-aware trace-driven simulations. VLSI-SoC 2010: 229-234 - Marc Pons, Francesc Moll, Antonio Rubio, Jaume Abella, Xavier Vera, Antonio González:
VCTA: A Via-Configurable Transistor Array regular fabric. VLSI-SoC 2010: 335-340 - François Poucheret, Lyonel Barthe, Pascal Benoit, Lionel Torres, Philippe Maurine, Michel Robert:
Spatial EM jamming: A countermeasure against EM Analysis? VLSI-SoC 2010: 105-110 - Joachim Neves Rodrigues, Omer Can Akgun, Viktor Öwall:
A < 1 pJ sub-VT cardiac event detector in 65 nm LL-HVT CMOS. VLSI-SoC 2010: 253-258