2022 export record
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conf/vlsit/GeumLJAKSKPBJK22 share record
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Dae-Myeong Geum , Jinha Lim , Junho Jang , Seungyeop Ahn , SeongKwang Kim , Joonsup Shim , Bong Ho Kim , Juhyuk Park , Woo Jin Baek , Jaeyong Jeong , Sanghyeon Kim : A sub-micron-thick InGaAs broadband (400-1700 nm) photodetectors with a high external quantum efficiency (>70%). VLSI Technology and Circuits 2022 : 413-414 export record
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conf/vlsit/KitamuraKHBKKTT22 share record
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Shota Kitamura , Naohiko Kimizuka , Akiko Honjo , Koichi Baba , Toshihiro Kurobe , Hideomi Kumano , Takuya Toyofuku , Kouhei Takeuchi , Shota Nishimura , Akihiko Kato , Tomoyuki Hirano , Yusuke Oike : Low-Noise Multi-Gate Pixel Transistor for Sub-Micron Pixel CMOS Image Sensors. VLSI Technology and Circuits 2022 : 347-348 2019 export record
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journals/ejisdc/Ilavarasan19 share record
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P. Vigneswara Ilavarasan : Present and future of the use and impact of information and communication technology in informal microenterprises: Insights from India. Electron. J. Inf. Syst. Dev. Ctries. 85 (3 ) (2019 )share record
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Swatilekha Majumdar : A Novel Gate-Level On-Chip Crosstalk Noise Reduction Circuit for Deep Sub-micron Technology. VDAT 2019 : 171-179 2018 export record
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conf/miipop/JacksonHPKS18 share record
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Pamela R. Jackson , Andrea Hawkins-Daarud , Savannah C. Partridge , Paul E. Kinahan , Kristin R. Swanson : Simulating magnetic resonance images based on a model of tumor growth incorporating microenvironment. Medical Imaging: Image Perception, Observer Performance, and Technology Assessment 2018 : 105771D 2016 export record
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journals/mr/OhyamaNMSNSS16 share record
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Masaki Ohyama , Masatsugu Nimura , Jun Mizuno , Shuichi Shoji , Toshihisa Nonaka , Yoichi Shinba , Akitsu Shigetou : Evaluation of hybrid bonding technology of single-micron pitch with planar structure for 3D interconnection. Microelectron. Reliab. 59 : 134-139 (2016 )export record
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conf/glvlsi/ChakrabortyKASM16 share record
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Tuhin Subhra Chakraborty , Santanu Kundu , Deepak Agrawal , Sanjay Tanaji Shinde , Jacob Mathews , Rekha K. James : Leakage Power Minimization in Deep Sub-Micron Technology by Exploiting Positive Slacks of Dependent Paths. ACM Great Lakes Symposium on VLSI 2016 : 365-368 2015 share record
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Indranil Roy : Algorithmic techniques for the micron automata processor. Georgia Institute of Technology, Atlanta, GA, USA, 2015 export record
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journals/integration/Asyaei15 share record
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Mohammad Asyaei : A new leakage-tolerant domino circuit using voltage-comparison for wide fan-in gates in deep sub-micron technology. Integr. 51 : 61-71 (2015 )share record
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Satjana Pattanasak , Wibool Piyawattanametha : Light microendoscopy with MEMS technology. NEMS 2015 : 550-552 2014 share record
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Szymon Bugiel , Roma Dasgupta , Sebastian Glab , Marek Idzik , Piotr Kapusta : Development of pixel detector in Novel sub-micron technology SOI CMOS 200 nm. MIXDES 2014 : 205-208 export record
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conf/mixdes/DasguptaBGIMK14 share record
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Roma Dasgupta , Szymon Bugiel , Sebastian Glab , Marek Idzik , Jakub Moron , Piotr Kapusta : Design and simulations of the 10-bit SAR ADC in novel sub-micron technology 200 nm SOI CMOS. MIXDES 2014 : 175-179 2013 share record
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Halil Tekin : Microengineered responsive platforms for spatial and geometrical control of multicellular organizations. Massachusetts Institute of Technology, Cambridge, MA, USA, 2013 export record
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journals/ieiceee/ZhangDZ13 share record
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Qi-Sheng Zhang , Ming Deng , Qimao Zhang : A high DC-gain low-power current recycling amplifier in deep sub-micron technology. IEICE Electron. Express 10 (19 ) : 20130624 (2013 )share record
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Ishraga Khattab : Microenterprises marketing problems and technology prospective. Int. J. Bus. Inf. Syst. 12 (3 ) : 259-270 (2013 )export record
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conf/vdat/MaheshwariRKG13 share record
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Sachin Maheshwari , Rameez Raza , Pramod Kumar , Anu Gupta : Convex Optimization of Energy and Delay Using Logical Effort Method in Deep Sub-micron Technology. VDAT 2013 : 185-193 share record
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Himadri Singh Raghav , Sachin Maheshwari , B. Prasad Singh : Performance Analysis of Subthreshold 32-Bit Kogge-Stone Adder for Worst-Case-Delay and Power in Sub-micron Technology. VDAT 2013 : 100-107 2011 share record
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Ijeoma Sandra Irobi : Analysis and Test Development for Parasitic Fails in Deep Sub-Micron Memory Devices. Delft University of Technology, Netherlands, 2011 share record
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Suwen Yang , Ian W. Jones , Mark R. Greenstreet : Synchronizer Performance in Deep Sub-Micron Technology. ASYNC 2011 : 33-42 share record
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Chun Zhao , W. Pan , C. Z. Zhao , Ka Lok Man , J. Choi , J. Chang : Performance-effective compaction of standard cell library for edge-triggered latches utilizing 0.5 micron technology. ISOCC 2011 : 313-316 2010 share record
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M. Reza Javaheri , Reza Sedaghat : Strength violation effect on soft-error detection in sub-micron technology. Microelectron. Reliab. 50 (7 ) : 971-977 (2010 )share record
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Travis Good , Mehruz Kamal , Sajda Qureshi , Nancy Jimenez : Information Technology Adoption in Latin American Microenterprises. AMCIS 2010 : 498 share record
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Samiran DasGupta , Pradip Mandal : An Improvised MOS Transistor Model Suitable for Geometric Program Based Analog Circuit Sizing in Sub-micron Technology. VLSI Design 2010 : 294-299 2009 export record
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journals/jssc/OjeforsPLR09 share record
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Erik Öjefors , Ullrich R. Pfeiffer , Alvydas Lisauskas , Hartmut G. Roskos : A 0.65 THz Focal-Plane Array in a Quarter-Micron CMOS Process Technology. IEEE J. Solid State Circuits 44 (7 ) : 1968-1976 (2009 )export record
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journals/mr/GalyDVREJPB09 share record
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Philippe Galy , Sylvain Dudit , Michel Vallet , Corinne Richier , Christophe Entringer , Frank Jezequel , E. Petit , J. Beltritti : Impact and damage on deep sub-micron CMOS technology induced by substrate current due to ESD stress. Microelectron. Reliab. 49 (9-11 ) : 1107-1110 (2009 )2007 share record
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Hung-Sung Lin , Chun-Ming Chen , Kuo-Hsiung Chen , Afung Wang , C. H. Chao : A case study of defects due to process marginalities in deep sub-micron technology. Microelectron. Reliab. 47 (9-11 ) : 1604-1608 (2007 )2006 share record
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Niladri Roy , Mani Najmabadi , Rabin Raut , Vijay Kumar Devabhaktuni : A Systematic Approach Towards the Implementation of a Low-Noise Amplifier in Sub-Micron CMOS Technology. CCECE 2006 : 1909-1913 share record
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Sanjeev K. Jain , Pankaj Agarwal : A Low Leakage and SNM Free SRAM Cell Design in Deep Sub Micron CMOS Technology. VLSI Design 2006 : 495-498 2005 share record
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Nicolle Wilke , A. Mulcahy , S.-R. Ye , A. Morrissey : Process optimization and characterization of silicon microneedles fabricated by wet etch technology. Microelectron. J. 36 (7 ) : 650-656 (2005 )