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ORCIDNaoyuki Kawabe
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2010 – 2019
- 2018
[j4]Kentaro Yoshioka
, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Masatoshi Hirono, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiko Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto:
A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC. IEEE J. Solid State Circuits 53(11): 3026-3038 (2018)- [c7]Kentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiro Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto:
A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique. ISSCC 2018: 92-94
2000 – 2009
- 2007
- [c6]Mototsugu Hamada, Takeshi Kitahara, Naoyuki Kawabe, Hironori Sato, Tsuyoshi Nishikawa, Takayoshi Shimazawa, Takahiro Yamashita, Hiroyuki Hara, Yukihito Oowaki:
An automated runtime power-gating scheme. ICCD 2007: 382-387 - [i1]Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa:
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction. CoRR abs/0710.4762 (2007) - 2006
- [j3]Toshihide Fujiyoshi, Shinichiro Shiratake, Shuou Nomura, Tsuyoshi Nishikawa, Yoshiyuki Kitasho, Hideho Arakida, Yuji Okuda, Yoshiro Tsuboi, Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Fumitoshi Hatori, Takayoshi Shimazawa, Kunihiko Yahagi, Hideki Takeda, Masami Murakata, Fumihiro Minami, Naoyuki Kawabe, Takeshi Kitahara, Katsuhiro Seta, Masafumi Takahashi, Yukihito Oowaki, Tohru Furuyama:
A 63-mW H.264/MPEG-4 audio/visual codec LSI with module-wise dynamic Voltage/frequency scaling. IEEE J. Solid State Circuits 41(1): 54-62 (2006) - 2005
- [c5]Mototsugu Hamada, Hiroyuki Hara, Tetsuya Fujita, Chen Kong Teh, Takayoshi Shimazawa, Naoyuki Kawabe, Takeshi Kitahara, Yu Kikuchi, Tsuyoshi Nishikawa, Makoto Takahashi, Yukihito Oowaki:
A conditional clocking flip-flop for low power H.264/MPEG-4 audio/visual codec LSI. CICC 2005: 527-530 - [c4]Takeshi Kitahara, Naoyuki Kawabe, Fumihiro Minami, Katsuhiro Seta, Toshiyuki Furusawa:
Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction. DATE 2005: 646-647 - 2002
- [j2]Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa:
Selective Multi-Threshold Technique for High-Performance and Low-Standby Applications. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2667-2673 (2002) - [j1]Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak:
Code Coverage-Based Power Estimation Techniques for Microprocessors. J. Circuits Syst. Comput. 11(5): 557- (2002) - [c3]Kimiyoshi Usami, Naoyuki Kawabe, Masayuki Koizumi, Katsuhiro Seta, Toshiyuki Furusawa:
Automated selective multi-threshold design for ultra-low standby applications. ISLPED 2002: 202-206 - 2000
- [c2]Naoyuki Kawabe, Kimiyoshi Usami:
Low-power technique for on-chip memory using biased partitioning and access concentration. CICC 2000: 275-278 - [c1]Gang Qu, Naoyuki Kawabe, Kimiyoshi Usami, Miodrag Potkonjak:
Function-level power estimation methodology for microprocessors. DAC 2000: 810-813
Coauthor Index
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