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2020 – today
- 2023
[j9]Seongun Bae
, Minseob Lee, Sang-Min Yoo, Jae-Yoon Sim:
A Temperature Compensated Ring Oscillator With LC-Based Period Error Detection. IEEE Trans. Very Large Scale Integr. Syst. 31(12): 2152-2156 (2023)- 2021
- [j8]Shih-Chang Hung, Si-Wook Yoo, Sang-Min Yoo:
A Quadrature Class-G Complex-Domain Doherty Digital Power Amplifier. IEEE J. Solid State Circuits 56(7): 2029-2039 (2021) - 2020
- [j7]Si-Wook Yoo, Shih-Chang Hung, Sang-Min Yoo:
A Multimode Multi-Efficiency-Peak Digital Power Amplifier. IEEE J. Solid State Circuits 55(12): 3322-3334 (2020) - [c10]Si-Wook Yoo, Shih-Chang Hung, Jeffrey S. Walling, David J. Allstot, Sang-Min Yoo:
10.7 A 0.26mm2 DPD-Less Quadrature Digital Transmitter With 30dB Pout Range in 65nm CMOS. ISSCC 2020: 184-186 - [c9]Si-Wook Yoo, Shih-Chang Hung, Sang-Min Yoo:
24.4 A Watt-Level Multimode Multi-Efficiency-Peak Digital Polar Power Amplifier with Linear Single-Supply Class-G Technique. ISSCC 2020: 368-370
2010 – 2019
- 2019
- [j6]Si-Wook Yoo, Shih-Chang Hung, Sang-Min Yoo:
A Watt-Level Quadrature Class-G Switched-Capacitor Power Amplifier With Linearization Techniques. IEEE J. Solid State Circuits 54(5): 1274-1287 (2019) - 2013
- [j5]Sang-Min Yoo, Jeffrey S. Walling, Ofir Degani, Benjamin Jann, Ram Sadhwani, Jacques Christophe Rudell, David J. Allstot:
A Class-G Switched-Capacitor RF Power Amplifier. IEEE J. Solid State Circuits 48(5): 1212-1224 (2013) - 2012
- [j4]Jeffrey S. Walling, Sang-Min Yoo, David J. Allstot:
Digital power amplifier: A new way to exploit the switched-capacitor circuit. IEEE Commun. Mag. 50(4): 145-151 (2012) - 2011
- [j3]Sang-Min Yoo, Jeffrey S. Walling, Eum Chan Woo, Benjamin Jann, David J. Allstot:
A Switched-Capacitor RF Power Amplifier. IEEE J. Solid State Circuits 46(12): 2977-2987 (2011) - [c8]Karthik Natarajan, Sang-Min Yoo, David J. Allstot, Jeffrey S. Walling:
Towards greener wireless transmission: Efficient power amplifier design. IGCC 2011: 1-4 - [c7]Sang-Min Yoo, Jeffrey S. Walling, Eum Chan Woo, David J. Allstot:
A switched-capacitor power amplifier for EER/polar transmitters. ISSCC 2011: 428-430
2000 – 2009
- 2006
- [c6]Tae-Hwan Oh, Sang-Min Yoo, Kyoung-Ho Moon, Jae-Whui Kim:
A 3.0 V 72mW 10b 100 MSample/s Nyquist-rate CMOS pipelined ADC in 0.54 mm2. ISCAS 2006 - [c5]Sang-Min Yoo, Tae-Hwan Oh, Ho-Young Lee, Kyung-Ho Moon, Jae-Whui Kim:
A 3.0V 12b 120 Msample/s CMOS pipelined ADC. ISCAS 2006 - [c4]Hee-Cheol Choi, Ju-Wha Kim, Sang-Min Yoo, Kang-Jin Lee, Tae-Hwan Oh, Mi-Jung Seo, Jae-Whui Kim:
A 15mW 0.2mm2 50MS/s ADC with wide input range. ISSCC 2006: 842-851 - 2004
- [j2]Jong-Bum Park, Sang-Min Yoo, Se-Won Kim, Young-Jae Cho, Seung-Hoon Lee:
A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth. IEEE J. Solid State Circuits 39(8): 1335-1337 (2004) - [j1]Sang-Min Yoo, Jong-Bum Park, Seung-Hoon Lee, Un-Ku Moon:
A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching. IEEE Trans. Circuits Syst. II Express Briefs 51-II(5): 269-275 (2004) - 2002
- [c3]Sang-Min Yoo, Tae-Hwan Oh, Jung-Woong Moon, Seung-Hoon Lee, Un-Ku Moon:
A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR. CICC 2002: 441-444 - 2000
- [c2]Young-Deuk Jeon, Byeong-Lyeol Jeon, Seung-Chul Lee, Sang-Min Yoo, Seung-Hoon Lee:
A 12b 50 MHz 3.3V CMOS acquisition time minimized A/D converter. ASP-DAC 2000: 613-616 - [c1]Young-Deuk Jeon, Seung-Chul Lee, Sang-Min Yoo, Seung-Hoon Lee:
Acquisition-time minimization and merged-capacitor switching techniques for sampling-rate and resolution improvement of CMOS ADCs. ISCAS 2000: 451-454
Coauthor Index
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