"Reveal: A Formal Verification Tool for Verilog Designs."

Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah (2008)

Details and statistics

DOI: 10.1007/978-3-540-89439-1_25

access: closed

type: Conference or Workshop Paper

metadata version: 2017-05-23

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