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ORCIDKunihiro Fujiyoshi
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Journal Articles
- 2024
[j19]Arata Kaneko, Htoo Htoo Sandi Kyaw, Kunihiro Fujiyoshi, Keiichi Kaneko:
Node-to-Node and Node-to-Set Disjoint Paths Problems in Bicubes. IEICE Trans. Inf. Syst. 107(9): 1133-1139 (2024)- 2017
- [j18]Kunihiro Fujiyoshi, Takahisa Imano:
Photo-Diode Array Partitioning Problem for a Rectangular Region. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 100-A(12): 2851-2856 (2017) - 2014
- [j17]Keitaro Ue, Kunihiro Fujiyoshi:
A Method of Analog IC Placement with Common Centroid Constraints. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 97-A(1): 339-346 (2014) - 2010
- [j16]Hidenori Ohta, Toshinori Yamada, Kunihiro Fujiyoshi:
On the Number of Rooms in a Rectangular Solid Dissection. Inf. Media Technol. 5(2): 434-442 (2010) - [j15]Hidenori Ohta, Toshinori Yamada, Kunihiro Fujiyoshi:
On the Number of Rooms in a Rectangular Solid Dissection. J. Inf. Process. 18: 138-146 (2010) - 2009
- [j14]Natsumi Hirakawa, Kunihiro Fujiyoshi:
Placement with Symmetry Constraints for Analog IC Layout Design Based on Tree Representation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 92-A(2): 467-474 (2009) - [j13]Kunihiro Fujiyoshi, Hidenori Kawai, Keisuke Ishihara:
A Tree Based Novel Representation for 3D-Block Packing. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 759-764 (2009) - 2008
- [j12]Hidenori Ohta, Toshinori Yamada, Chikaaki Kodama
, Kunihiro Fujiyoshi:
The O-Sequence: Representation of 3D-Dissection. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 91-A(8): 2111-2119 (2008) - 2007
- [j11]Kunihiro Fujiyoshi, Chikaaki Kodama, Akira Ikeda:
A fast algorithm for rectilinear block packing based on selected sequence-pair. Integr. 40(3): 274-284 (2007) - [j10]Shinichi Koda, Chikaaki Kodama, Kunihiro Fujiyoshi:
Linear Programming-Based Cell Placement With Symmetry Constraints for Analog IC Layout. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(4): 659-668 (2007) - 2005
- [j9]Chikaaki Kodama, Kunihiro Fujiyoshi:
Minimizing the Number of Empty Rooms on Floorplan by Dissection Line Merge. IEICE Trans. Inf. Syst. 88-D(7): 1389-1396 (2005) - [j8]Hiroaki Itoga, Chikaaki Kodama, Kunihiro Fujiyoshi:
A Graph Based Soft Module Handling in Floorplan. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3390-3397 (2005) - 2003
- [j7]Kazuya Wakata, Hiroaki Saito, Kunihiro Fujiyoshi, Keishi Sakanushi, Takayuki Obata, Chikaaki Kodama:
An Improved Method of Convex Rectilinear Block Packing Based on Sequence-Pair. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 86-A(12): 3148-3157 (2003) - 2002
- [j6]Chikaaki Kodama, Kunihiro Fujiyoshi:
An Efficient Decoding Method of Sequence-Pair with Reduced Redundancy. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 85-A(12): 2785-2794 (2002) - 2000
- [j5]Kunihiro Fujiyoshi, Hiroshi Murata:
Arbitrary convex and concave rectilinear block packing usingsequence-pair. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(2): 224-233 (2000) - 1998
- [j4]Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko:
VLSI/PCB placement with obstacles based on sequence pair. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(1): 60-68 (1998) - [j3]Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani:
Module packing based on the BSG-structure and IC layout applications. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 17(6): 519-530 (1998) - 1997
- [j2]Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu:
Design of minimum and uniform bipartites for optimum connection blocks of FPGA. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(11): 1377-1383 (1997) - 1996
- [j1]Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani:
VLSI module placement based on rectangle-packing by the sequence-pair. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 15(12): 1518-1524 (1996)
Conference and Workshop Papers
- 2023
- [c23]Kunihiro Fujiyoshi, Tomoya Masutani:
A Necessary and Sufficient Condition to Generate Representative Clip for Edge-Constrained Clustering of Layout Pattern Classification Problem. NEWCAS 2023: 1-4 - 2016
- [c22]Kunihiro Fujiyoshi, Takahisa Imano:
A method for photo-diode array partitioning problem. MWSCAS 2016: 1-4 - 2014
- [c21]Kenichiro Murotatsu, Kunihiro Fujiyoshi:
Adjacent common centroid placement for analog IC layout design. APCCAS 2014: 619-622 - [c20]Kunihiro Fujiyoshi, Keitaro Ue:
Average placement method with common centroid constraints for analog IC layout design. MWSCAS 2014: 226-229 - 2012
- [c19]Hiroshi Tezuka, Kunihiro Fujiyoshi:
An efficient solution space for floorplan of 3D-LSI. ICECS 2012: 460-463 - 2011
- [c18]Kunihiro Fujiyoshi, Keisuke Ishihara, Tan Wei Liang:
A novel representation for repeated placement. ISCAS 2011: 2869-2872 - 2009
- [c17]Hidenori Ohta, Kunihiro Fujiyoshi:
Representation of 3D-LSI Floorplan based on Stacked-rectangular-dissection. ISCAS 2009: 1731-1734 - 2007
- [c16]Kunihiro Fujiyoshi, Hidenori Kawai, Keisuke Ishihara:
DTS: A Tree Based Representation for 3D-Block Packing. ISCAS 2007: 1045-1048 - 2006
- [c15]Norihide Okada, Chikaaki Kodama, Takashi Sato, Kunihiro Fujiyoshi:
Thermal Driven Module Placement Using Sequence-pair. APCCAS 2006: 1871-1874 - [c14]Yukihide Kohira, Chikaaki Kodama, Kunihiro Fujiyoshi, Atsushi Takahashi:
Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems. ISCAS 2006 - [c13]Shinichi Kouda, Chikaaki Kodama, Kunihiro Fujiyoshi:
Improved method of cell placement with symmetry constraints for analog IC layout design. ISPD 2006: 192-199 - 2004
- [c12]Chikaaki Kodama, Kunihiro Fujiyoshi, Teppei Koga:
A novel encoding method into sequence-pair. ISCAS (5) 2004: 329-332 - 2003
- [c11]Chikaaki Kodama, Kunihiro Fujiyoshi:
Selected sequence-pair: an efficient decodable packing representation in linear time using sequence-pair. ASP-DAC 2003: 331-337 - 2002
- [c10]Hiroaki Saito, Kazuya Wakata, Kunihiro Fujiyoshi, Keishi Sakanushi, Takayuki Obata:
An improved method of convex-shaped block packing based on sequence-pair [VLSI layout]. APCCAS (2) 2002: 125-130 - [c9]Chikaaki Kodama, Kunihiro Fujiyoshi:
An efficient decoding method of sequence-pair. APCCAS (2) 2002: 131-136 - 2000
- [c8]Koji Kiyota, Kunihiro Fujiyoshi:
Simulated annealing search through general structure floorplans using sequence-pair. ISCAS 2000: 77-80 - 1999
- [c7]Kunihiro Fujiyoshi, Hiroshi Murata:
Arbitrary convex and concave rectilinear block packing using sequence-pair. ISPD 1999: 103-110 - 1997
- [c6]Hiroshi Murata, Kunihiro Fujiyoshi, Tomomi Watanabe, Yoji Kajitani:
A mapping from sequence-pair to rectangular dissection. ASP-DAC 1997: 625-633 - [c5]Hiroshi Murata, Kunihiro Fujiyoshi, Mineo Kaneko:
VLSI/PCB placement with obstacles based on sequence-pair. ISPD 1997: 26-31 - 1996
- [c4]Shigetoshi Nakatake, Kunihiro Fujiyoshi, Hiroshi Murata, Yoji Kajitani:
Module placement on BSG-structure and IC layout applications. ICCAD 1996: 484-491 - 1995
- [c3]Hiroshi Murata, Kunihiro Fujiyoshi, Shigetoshi Nakatake, Yoji Kajitani:
Rectangle-packing-based module placement. ICCAD 1995: 472-479 - 1994
- [c2]Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu:
The Totally-Perfect Bipartite Graph and Its Construction. ISAAC 1994: 541-549 - [c1]Kunihiro Fujiyoshi, Yoji Kajitani, Hiroshi Niitsu:
Design of Optimum Totally Perfect Connection-Blocks of FPGA. ISCAS 1994: 221-224
Coauthor Index
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