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ORCIDTetsuro Matsuno
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Journal Articles
- 2010
[j5]Tetsuro Matsuno, Daisuke Kosaka, Makoto Nagata
:
Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 93-A(2): 440-447 (2010)- [j4]Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata:
An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology. IEICE Trans. Electron. 93-C(6): 820-826 (2010) - 2006
- [j3]Junichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masayuki Miyama, Masahiko Yoshimoto:
A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 89-A(12): 3623-3633 (2006) - 2005
- [j2]Junichi Miyakoshi, Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Masayuki Miyama, Masahiko Yoshimoto:
A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation. IEICE Trans. Electron. 88-C(4): 559-569 (2005) - [j1]Yuichiro Murachi, Koji Hamano, Tetsuro Matsuno, Junichi Miyakoshi, Masayuki Miyama, Masahiko Yoshimoto:
A 95 mW MPEG2 MP@HL Motion Estimation Processor Core for Portable High-Resolution Video Application. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. 88-A(12): 3492-3499 (2005)
Conference and Workshop Papers
- 2009
- [c3]Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata:
A 6-bit arbitrary digital noise emulator in 65nm CMOS technology. CICC 2009: 187-190 - 2007
- [c2]Mitsuya Fukazawa, Tetsuro Matsuno, Toshifumi Uemura, Rei Akiyama, Tetsuya Kagemoto, Hiroshi Makino, Hidehiro Takata, Makoto Nagata:
Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs. ISSCC 2007: 288-603 - 2006
- [c1]Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno:
A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing. VLSI-SoC 2006: 192-197
Coauthor Index
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