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ORCIDGe Zhang 0007
Person information
- affiliation: Chinese Academy of Sciences, Institute of Computing Technology, Key Laboratory of Computer System and Architecture, Beijing, China
Other persons with the same name
- Ge Zhang — disambiguation page
- Ge Zhang 0001 — Karlstad University, Karlstad, Sweden
- Ge Zhang 0002
![[0000-0001-6009-780X]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0001-6009-780X")
— Macquarie University, Sydney, NSA, Australia - Ge Zhang 0003 — Massachusetts Institute of Technology, MIT, Department of Chemical Engineering, Cambridge, MA, USA
- Ge Zhang 0004 — Xinjiang University, Urumqi, China
- Ge Zhang 0005 — University of Kaiserslautern, Department of Computer Science, Integrated Communication Systems Lab, Germany
- Ge Zhang 0006 — Northwestern Polytechnical University, School of Electronics and Information, Xi'an, China
- Ge Zhang 0008 — Henan University of Chinese Medicine, School of Information Engineering, Zhengzhou, China (and 1 more)
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2010 – 2019
- 2010
[c9]Jun Xu, Ge Zhang, Weiwu Hu:
Optimizing power and throughput for m-out-of-n encoded asynchronous circuits. ISQED 2010: 151-157- [c8]Zichu Qi, Qi Guo, Ge Zhang, Xiangku Li, Weiwu Hu:
Design of Low-Cost High-Performance Floating-Point Fused Multiply-Add with Reduced Power. VLSI Design 2010: 206-211
2000 – 2009
- 2008
- [c7]Jun Wang, Hongbo Zeng, Kun Huang, Ge Zhang, Yan Tang:
Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor. DATE 2008: 792-795 - [c6]Hongbo Zeng, Jun Wang, Ge Zhang, Weiwu Hu:
An interconnect-aware power efficient cache coherence protocol for CMPs. IPDPS 2008: 1-11 - [c5]Qifei Fan, Ge Zhang, Weiwu Hu:
A synchronized variable frequency clock scheme in chip multiprocessors. ISCAS 2008: 3410-3413 - 2007
- [c4]Xiaotao Chang, Mingming Zhang, Ge Zhang, Zhimin Zhang, Jun Wang:
Adaptive Clock Gating Technique for Low Power IP Core in SoC Design. ISCAS 2007: 2120-2123 - [c3]Jun Wang, Ge Zhang, Weiwu Hu:
An Efficient Error Control Scheme for Chip-to-Chip Optical Interconnects. ISCAS 2007: 3712-3715 - [c2]Mingming Zhang, Xiaotao Chang, Ge Zhang:
Reducing cache energy consumption by tag encoding in embedded processors. ISLPED 2007: 367-370 - 2006
- [j1]Ge Zhang, Weiwu Hu, Zichu Qi:
Parallel Error Detection for Leading Zero Anticipation. J. Comput. Sci. Technol. 21(6): 901-906 (2006) - 2005
- [c1]Ge Zhang, Zichu Qi, Weiwu Hu:
A novel design of leading zero anticipation circuit with parallel error detection. ISCAS (1) 2005: 676-679
Coauthor Index
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