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Meng-Hung Shen
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Journal Articles
- 2015
- [j6]Jen-Huan Tsai, Sheng-An Ko, Chia-Wei Wang, Yang-Chi Yen, Hui-Huan Wang, Po-Chiun Huang, Po-Hsiang Lan, Meng-Hung Shen:
A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics. IEEE J. Solid State Circuits 50(11): 2533-2548 (2015) - [j5]Meng-Hung Shen, Po-Chiun Huang:
A Wide-Range Multiport LC-Ladder Oscillator and Its Applications to a 1.2-10.1 GHz PLL. IEEE Trans. Very Large Scale Integr. Syst. 23(1): 184-188 (2015) - 2014
- [j4]Jen-Huan Tsai, Hui-Huan Wang, Yen-Ju Chen, Yen-Hsin Wei, Yo-Hsien Kao, Yang-Chi Yen, Po-Chiun Huang, Meng-Hung Shen, Hsin Chen:
A 1-V-0.6-V 9-b 1.5-MS/s Reference-Free Charge-Sharing SAR ADC for Wireless-Powered Implantable Telemetry. IEEE Trans. Circuits Syst. II Express Briefs 61-II(11): 825-829 (2014) - 2012
- [j3]Meng-Hung Shen, Po-Chiun Huang:
A Low Cost Calibrated DAC for High-Resolution Video Display System. IEEE Trans. Very Large Scale Integr. Syst. 20(9): 1743-1747 (2012) - 2010
- [j2]Meng-Hung Shen, Jen-Huan Tsai, Po-Chiun Huang:
Random Swapping Dynamic Element Matching Technique for Glitch Energy Minimization in Current-Steering DAC. IEEE Trans. Circuits Syst. II Express Briefs 57-II(5): 369-373 (2010) - 2008
- [j1]Meng-Hung Shen, Po-Hsiang Lan, Po-Chiun Huang:
A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops. IEEE Trans. Circuits Syst. II Express Briefs 55-II(5): 409-413 (2008)
Conference and Workshop Papers
- 2013
- [c4]Don Chih-Liang Chen, Jiann-Tyng Tzeng, David Barry Scott, Shih Wei Peng, Meng-Hung Shen, Kam Tou Sio, Praneeth Narayanasetti:
Optimization processing unit (OPU) applied to integrated circuit design and manufacturing. CASE 2013: 1008-1015 - 2012
- [c3]Jen-Huan Tsai, Yen-Ju Chen, Yan-Fong Lai, Meng-Hung Shen, Po-Chiun Huang:
A 14-bit 200MS/s current-steering DAC achieving over 82dB SFDR with digitally-assisted calibration and dynamic matching techniques. VLSI-DAT 2012: 1-4 - 2011
- [c2]Chang-Ming Lai, Meng-Hung Shen, Geng-Yi Pan, Po-Chiun Huang:
A 90nm CMOS, 5.6ps, 0.23pJ/code time-to-digital converter with multipath oscillator and seamless cycle detection. A-SSCC 2011: 357-360 - [c1]Chang-Ming Lai, Meng-Hung Shen, Yi-Da Wu, Kai-Hsiang Huang, Po-Chiun Huang:
A 0.24 to 2.4 GHz phase-locked loop with low supply sensitivity in 0.18-µm CMOS. ISCAS 2011: 981-984
Coauthor Index
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