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Po-Hsiang Lan
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2010 – 2019
- 2016
- [j5]Po-Chiun Huang, Shin-Jie Huang, Po-Hsiang Lan:
Cooperation between Distributed Power Modules for SoC Power Management. IEICE Trans. Electron. 99-C(6): 606-613 (2016) - 2015
- [j4]Jen-Huan Tsai, Sheng-An Ko, Chia-Wei Wang, Yang-Chi Yen, Hui-Huan Wang, Po-Chiun Huang, Po-Hsiang Lan, Meng-Hung Shen:
A 1 V Input, 3 V-to-6 V Output, 58%-Efficient Integrated Charge Pump With a Hybrid Topology for Area Reduction and an Improved Efficiency by Using Parasitics. IEEE J. Solid State Circuits 50(11): 2533-2548 (2015) - 2013
- [j3]Po-Hsiang Lan, Tsung-Ju Yang, Po-Chiun Huang:
A High-Efficiency, Wide Workload Range, Digital Off-Time Modulation (DOTM) DC-DC Converter With Asynchronous Power Saving Technique. IEEE Trans. Very Large Scale Integr. Syst. 21(1): 67-77 (2013) - 2012
- [j2]Po-Hsiang Lan, Po-Chiun Huang:
A High Efficiency FLL-Assisted Current-Controlled DC-DC Converter Over Light-Loaded Range. IEEE Trans. Circuits Syst. I Regul. Pap. 59-I(10): 2468-2476 (2012) - [c3]Po-Hsiang Lan, Yao-Jun Kuo, Po-Chiun Huang:
An area-efficient CMOS switching converter with on-chip LC filter using feedforward ripple cancellation technique. VLSI-DAT 2012: 1-4 - 2011
- [c2]Po-Hsiang Lan, Tsung-Ju Yang, Po-Chiun Huang:
An asynchronous digitally-controlled switching converter with adaptive resolution and dynamic power saving to achieve higher than 93.5% efficiency between 5mA and 250mA load. A-SSCC 2011: 45-48 - 2010
- [c1]Po-Hsiang Lan, Chun-Yen Tseng, Po-Chiun Huang:
Design of a process-insensitive digital controller for high-frequency DC-DC SMPS. APCCAS 2010: 484-487
2000 – 2009
- 2008
- [j1]Meng-Hung Shen, Po-Hsiang Lan, Po-Chiun Huang:
A 1-V CMOS Pseudo-Differential Amplifier With Multiple Common-Mode Stabilization and Frequency Compensation Loops. IEEE Trans. Circuits Syst. II Express Briefs 55-II(5): 409-413 (2008)
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