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ORCIDPritha Banerjee 0001
Person information
- affiliation: University of Calcutta, India
Other persons with the same name
- Pritha Banerjee 0002
![[0000-0003-3691-638X]](https://dblp.uni-trier.de/img/orcid-mark.12x12.png "0000-0003-3691-638X")
— Jadavpur University, India
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2020 – today
- 2023
[j6]Sudipta Paul, Tridib Mukherjee, Pritha Banerjee, Susmita Sur-Kolay:
Concurrent Steiner Tree Selection for Global routing with EUVL Flare Reduction. Integr. 92: 66-76 (2023)- 2022
- [c10]Kritanta Saha, Pritha Banerjee, Susmita Sur-Kolay:
Stitch-avoiding Detailed Routing for Multiple E-Beam Lithography. VLSI-SoC 2022: 1-6 - [c9]Kritanta Saha, Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay:
Stitch-avoiding Global Routing for Multiple E-Beam Lithography. VLSID 2022: 138-143 - 2021
- [j5]Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay:
A study on flare minimisation in EUV lithography by post-layout re-allocation of wire segments. IET Circuits Devices Syst. 15(4): 310-329 (2021)
2010 – 2019
- 2019
- [c8]Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay:
Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and Dummification. ISVLSI 2019: 212-217 - 2017
- [c7]Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay:
Post-Layout Perturbation towards Stitch Friendly Layout for Multiple E-Beam Lithography. ICCD 2017: 411-414 - 2015
- [c6]Sudipta Paul, Pritha Banerjee, Susmita Sur-Kolay:
Flare reduction in EUV Lithography by perturbation of wire segments. VLSI-SoC 2015: 7-12 - 2013
- [c5]Tzu-Hen Lin, Pritha Banerjee, Yao-Wen Chang:
An efficient and effective analytical placer for FPGAs. DAC 2013: 10:1-10:6 - 2011
- [j4]Pritha Banerjee, Debasri Saha, Susmita Sur-Kolay:
Cone-based placement for field programmable gate arrays. IET Comput. Digit. Tech. 5(1): 49-62 (2011) - [j3]Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay:
Floorplanning for Partially Reconfigurable FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 30(1): 8-17 (2011)
2000 – 2009
- 2009
- [j2]Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu:
Fast Unified Floorplan Topology Generation and Sizing on Heterogeneous FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(5): 651-661 (2009) - [j1]Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu, Sandip Das, Subhas C. Nandy, Subhasis Bhattacharjee:
FPGA placement using space-filling curves: Theory meets practice. ACM Trans. Embed. Comput. Syst. 9(2): 12:1-12:23 (2009) - [c4]Pritha Banerjee, Megha Sangtani, Susmita Sur-Kolay:
Floorplanning for Partial Reconfiguration in FPGAs. VLSI Design 2009: 125-130 - 2007
- [c3]Pritha Banerjee, Susmita Sur-Kolay:
Faster Placer for Island-Style FPGAs. ICCTA 2007: 117-121 - [c2]Pritha Banerjee, Susmita Sur-Kolay, Arijit Bishnu:
Floorplanning in Modern FPGAs. VLSI Design 2007: 893-898 - 2005
- [c1]Pritha Banerjee, Subhasis Bhattacharjee, Susmita Sur-Kolay, Sandip Das, Subhas C. Nandy:
Fast FPGA Placement using Space-filling Curve. FPL 2005: 415-420
Coauthor Index
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