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"Design and FPGA implementation of digit-serial FIR filters."

Javier Valls et al. (1998)

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DOI: 10.1109/ICECS.1998.814860

access: closed

type: Conference or Workshop Paper

metadata version: 2021-06-11

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  dblp key:
  - conf/icecsys/VallsPSB98
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  - https://dblp.org/rec/conf/icecsys/VallsPSB98
Javier Valls, Marcos M. Peiró, Trinidad Sansaloni, Eduardo I. Boemo:
Design and FPGA implementation of digit-serial FIR filters. ICECS 1998: 191-194

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