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2020 – today
- 2024
[j25]Seungmyeong Cho
, Rina Yoon, Ilpyeong Yoon, Jihwan Moon, Seokjin Oh, Kyeong-Sik Min:
Optimization of Memristor Crossbar's Mapping Using Lagrange Multiplier Method and Genetic Algorithm for Reducing Crossbar's Area and Delay Time. Inf. 15(7): 409 (2024)- [j24]Youn-Hee Kim, Juwon Jun, You-Kyung Oh, Hee-Ji Choi, Mi-Jung Lee, Kyeong-Sik Min, Sung-Hyon Kim, Hyunseung Lee, Ho-Seok Nam, Son Singh, Byoung-Joon Kim, Jaegab Lee:
Assessing the Role of Yarn Placement in Plated Knit Strain Sensors: A Detailed Study of Their Electromechanical Properties and Applicability in Bending Cycle Monitoring. Sensors 24(5): 1690 (2024) - 2023
- [c16]Seokjin Oh, Rina Yoon, Seungmyeong Cho, Kyeong-Sik Min:
Hardware-Specific Optimization for Mapping of Convolutional Neural Networks to Memristor Crossbars. ASICON 2023: 1 - [c15]Seokjin Oh, Rina Yoon, Seungmyeong Cho, Kyeong-Sik Min:
Memristor Circuits for Non-Backpropagation Training Algorithm. ISOCC 2023: 201 - 2022
- [j23]Tien Van Nguyen, Jiyong An, Seokjin Oh, Son Ngoc Truong, Kyeong-Sik Min:
Quantization, training, parasitic resistance correction, and programming techniques of memristor-crossbar neural networks for edge intelligence. Neuromorph. Comput. Eng. 2(3): 32001 (2022) - [c14]Seokjin Oh, Jiyong An, Kyeong-Sik Min:
Neuron Deactivation Scheme for Defect-Tolerant Memristor Neural Networks. MOCAST 2022: 1-4 - 2021
- [c13]Tien Van Nguyen, Jiyong An, Kyeong-Sik Min:
Comparative Study on Quantization-Aware Training of Memristor Crossbars for Reducing Inference Power of Neural Networks at The Edge. IJCNN 2021: 1-6 - 2020
- [c12]Tien Van Nguyen, Ngoc-Thanh Le, Jiyong An, Kyeong-Sik Min:
Defect-Resilient Memristor Crossbar of Hierarchical Temporal Memory (HTM) Spatial Pooling for Near-IoT-Sensor Cognitive Computing. ICECS 2020: 1-4
2010 – 2019
- 2019
- [c11]Khoa Van Pham, Tien Van Nguyen, Kyeong-Sik Min:
Defect-Tolerant and Energy-Efficient Training of Multi-Valued and Binary Memristor Crossbars for Near-Sensor Cognitive Computing. ASICON 2019: 1-4 - [c10]Khoa Van Pham, Tien Van Nguyen, Kyeong-Sik Min:
Defect-Tolerant Crossbar Training of Memristor Ternary Neural Networks. ICECS 2019: 486-489 - [c9]Khoa Van Pham, Kyeong-Sik Min:
Non-Ideal Effects of Memristor-CMOS Hybrid Circuits for Realizing Multiple-Layer Neural Networks. ISCAS 2019: 1-5 - [p1]Fernando Corinto, Alon Ascoli, Young-Su Kim, Kyeong-Sik Min:
Cellular Nonlinear Networks with Memristor Synapses. Handbook of Memristor Networks 2019: 637-660 - 2016
- [j22]Son Ngoc Truong, Khoa Van Pham, Wonsun Yang, Sangho Shin, Ken Pedrotti, Kyeong-Sik Min:
New pulse amplitude modulation for fine tuning of memristor synapses. Microelectron. J. 55: 162-168 (2016) - [c8]Son Ngoc Truong, Khoa Van Pham, Wonsun Yang, Kyeong-Sik Min, Yawar Abbas, Chi Jung Kang:
Live demonstration: Memristor synaptic array with FPGA-implemented neurons for neuromorphic pattern recognition. APCCAS 2016: 742-743 - [c7]Son Ngoc Truong, Khoa Van Pham, Wonsun Yang, Kyeong-Sik Min:
Memristor circuits and systems for future computing and bio-inspired information processing. BioCAS 2016: 456-459 - 2015
- [c6]Son Ngoc Truong, SangHak Shin, JeaSang Song, Hyun-Sun Mo, Fernando Corinto, Kyeong-Sik Min:
Memristor-based cellular nanoscale networks: Theory, circuits, and applications. ISCAS 2015: 1134-1137 - 2012
- [j21]Eun-Sub Lee, Jun-Myung Choi, Young-Su Kim, Seok-Jin Ham, Jeong-Heon Kim, Sang-Don Byeon, Kyeong-Sik Min:
Sunlight-variation-adaptive charge pump circuit with self-reconfiguration for small-scale solar energy harvesting. IEICE Electron. Express 9(17): 1423-1433 (2012) - 2011
- [j20]Huan Minh Vo, Chul-Moon Jung, Eun-Sub Lee, Kyeong-Sik Min:
Dual-switch power gating revisited for small sleep energy loss and fast wake-up time in sub-45-nm nodes. IEICE Electron. Express 8(4): 232-238 (2011) - [j19]Eun-Sub Lee, Chul-Mun Jung, Huan Minh Vo, Kyeong-Sik Min:
Compact and efficient Maximum Power Point Tracking circuit for portable solar battery charger. IEICE Electron. Express 8(12): 930-937 (2011) - [j18]Huan Minh Vo, Chul-Moon Jung, Eun-Sub Lee, Kyeong-Sik Min:
Carry select adder with sub-block power gating for reducing active-mode leakage in sub-32-nm VLSIs. IEICE Electron. Express 8(16): 1322-1329 (2011) - [j17]Ji-Hye Bong, Kwan-Hee Jo, Kyeong-Sik Min, Sung-Mo Kang:
Oxide-Tunneling Leakage Suppressed SRAM for Sub-65-nm Very Large Scale Integrated Circuits. J. Low Power Electron. 7(1): 87-95 (2011) - [c5]Kwan-Hee Jo, Chul-Moon Jung, Kyeong-Sik Min:
Memristor models and circuits for controlling Process-VDD-Temperature variations. ASICON 2011: 283-286
2000 – 2009
- 2009
- [j16]Yong-Jin Kwon, Ji-Hye Bong, Dae Hwan Kim, Kyeong-Sik Min:
Sub-1-V-Output CMOS bandgap reference circuit with small area and low power consumption. IEICE Electron. Express 6(3): 161-166 (2009) - [j15]Ji-Hye Bong, Yong-Jin Kwon, Daejeong Kim, Kyeong-Sik Min:
Negative charge pump circuit with large output current and high power efficiency. IEICE Electron. Express 6(6): 304-309 (2009) - [j14]Kwan-Hee Jo, Ji-Hye Bong, Kyeong-Sik Min:
Low-power read circuit with self-adjusted column pulse width for diode-switch resistive RAMs. IEICE Electron. Express 6(14): 986-992 (2009) - [j13]Kwan-Hee Jo, Ji-Hye Bong, Kyeong-Sik Min, Sung-Mo Kang:
A compact Verilog-A model for Multi-Level-Cell Phase-change RAMs. IEICE Electron. Express 6(19): 1414-1420 (2009) - [c4]Ji-Hye Bong, Yong-Jin Kwon, Kyeong-Sik Min, Sung-Mo Kang:
New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs. ISQED 2009: 459-464 - 2008
- [j12]O-Sam Kwon, Yong-Jin Kwon, Ho-Jun Song, Kyeong-Sik Min:
Sense amplifier driving scheme with adaptive delay line for reducing peak current and driving time variations in deep-sub-micron DRAMs. IEICE Electron. Express 5(13): 472-477 (2008) - [j11]Duk-Hyung Lee, Daejeong Kim, Ho-Jun Song, Kyeong-Sik Min:
A Modified Dickson Charge Pump Circuit with High Efficiency and High Output Voltage. IEICE Trans. Electron. 91-C(2): 228-231 (2008) - [j10]Kyeong-Sik Min, Chul-Keun Park, Suk-Youb Kang:
History of Antenna Technology for Mobile Communications in Korea. IEICE Trans. Commun. 91-B(7): 2179-2186 (2008) - [j9]Duk-Hyung Lee, Dong-Kone Kwak, Kyeong-Sik Min:
Comparative Study on Leakage Current of Power-Gated SRAMs for 65-nm, 45-nm, 32-nm Technology Nodes. J. Comput. 3(3): 39-47 (2008) - 2007
- [j8]Jin-Gu Lee, Dae Hwan Kim, Jaegab Lee, Dong Myong Kim, Kyeong-Sik Min:
A compact HSPICE macromodel of resistive RAM. IEICE Electron. Express 4(19): 600-605 (2007) - [j7]Kyeong-Sik Min, Manh-Dat Vu:
An Approach for Numerical Analysis of Differential Equation-Based Feeding Point Modeling of Electromagnetic Devices. IEICE Trans. Commun. 90-B(5): 1208-1213 (2007) - [j6]O-Sam Kwon, Kyeong-Sik Min:
Fast-Delay and Low-Power Level Shifter for Low-Voltage Applications. IEICE Trans. Electron. 90-C(7): 1540-1543 (2007) - [c3]Duk-Hyung Lee, Dong-Kone Kwak, Kyeong-Sik Min:
Comparative Study on SRAMs for Suppressing Both Oxide-Tunneling Leakage and Subthreshold Leakage in Sub-70-nm Leakage Dominant VLSIs. VLSI Design 2007: 632-637 - 2006
- [j5]Kyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi, Takayasu Sakurai:
Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-VDD LSIs. IEEE Trans. Very Large Scale Integr. Syst. 14(4): 430-435 (2006) - 2005
- [j4]Kyeong-Sik Min, Kouichi Kanda, Hiroshi Kawaguchi, Kenichi Inagaki, Fayez Robert Saliba, Hoon-Dae Choi, Hyun-Young Choi, Daejeong Kim, Dong Myong Kim, Takayasu Sakurai:
Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's. IEICE Trans. Electron. 88-C(4): 760-767 (2005) - 2004
- [j3]Young-Jin Jeon, Joong-Ho Lee, Hyun-Chul Lee, Kyo-Won Jin, Kyeong-Sik Min, Jin-Yong Chung, Hong-June Park:
A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle clock dividers for production DDR SDRAMs. IEEE J. Solid State Circuits 39(11): 2087-2092 (2004) - [c2]Kyeong-Sik Min, Young-Hee Kim, Daejeong Kim, Dong Myeong Kim, Jin-Hong Ahn:
A large-current-output boosted voltage generator with non-overlapping clock control for sub-1-V memory applications. ASP-DAC 2004: 288-291 - 2002
- [j2]Jae-Kyung Wee, Kyeong-Sik Min, Jong-Tai Park, Sang-Pil Lee, Young-Hee Kim, Tae-Heum Yang, Jong-Doo Joo, Jin-Yong Chung:
A post-package bit-repair scheme using static latches with bipolar-voltage programmable antifuse circuit for high-density DRAMs. IEEE J. Solid State Circuits 37(2): 251-254 (2002) - [c1]Kyeong-Sik Min, Young-Hee Kim, Jin-Hong Ahn, Jin-Yong Chung, Takayasu Sakurai:
CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits. ISCAS (5) 2002: 545-548 - 2001
- [j1]Kyeong-Sik Min, Jin-Yong Chung:
A fast pump-down VBB generator for sub-1.5-V DRAMs. IEEE J. Solid State Circuits 36(7): 1154-1157 (2001)
Coauthor Index
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