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ORCIDEric Jia-Wei Fang
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- affiliation: MediaTek Inc., Hsinchu, Taiwan
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2020 – today
- 2024
[c21]Chien-Yu Lu, Bo-Jr Huang, Min-Chieh Chen, Ollie Tsai, Alfred Tsai, Eric Jia-Wei Fang, Yuju Cho, Harry H. Chen, Ping Kao, Ericbill Wang, Hugh Mair, Shih-Arn Hwang:
14.4 A Fully Digital Current Sensor Offering Per-Core Runtime Power for System Budgeting in a 4nm-Plus Octa-Core CPU. ISSCC 2024: 260-262- 2023
- [c20]Bo-Jr Huang, Alfred Tsai, Lear Hsieh, Kathleen Chang, C.-J. Tsai, Jia-Ming Chen, Eric Jia-Wei Fang, Sung S.-Y. Hsueh, Jack Ciao, Barry Chen, Chuck Chang, Ping Kao, Ericbill Wang, Harry H. Chen, Hugh Mair, Shih-Arn Hwang:
A 5G Mobile Gaming-Centric SoC with High-Performance Thermal Management in 4nm FinFET. ISSCC 2023: 40-41 - [c19]Kuan-Yu Lee
, Jia-Wei Fang, Yuan-Chun Sun, Cheng-Hsin Hsu:
Modeling Gamer Quality-of-Experience Using a Real Cloud VR Gaming Testbed. MMVE@MMSys 2023: 12-17 - [c18]Jia-Wei Fang, Kuan-Yu Lee, Teemu Kämäräinen, Matti Siekkinen, Cheng-Hsin Hsu:
Will Dynamic Foveation Boost Cloud VR Gaming Experience? NOSSDAV 2023: 29-35 - [c17]Chun Chen, Jeng-Yu Liao, James Chien-Mo Li, Harry H. Chen, Eric Jia-Wei Fang:
Vmin Prediction Using Nondestructive Stress Test. VTS 2023: 1-7 - 2022
- [c16]Wei-Chen Lin, Chun Chen, Chao-Ho Hsieh, James Chien-Mo Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh:
ML-Assisted VminBinning with Multiple Guard Bands for Low Power Consumption. ITC 2022: 213-218 - [c15]Sheng-Ming Tang, Yuan-Chun Sun, Jia-Wei Fang, Kuan-Yu Lee, Ching-Ting Wang, Cheng-Hsin Hsu:
Optimal Camera Placement for 6 Degree-of-Freedom Immersive Video Streaming Without Accessing 3D Scenes. IXR@MM 2022: 31-39 - [c14]Tzu-Yi Fan, Fangqi Liu, Jia-Wei Fang, Nalini Venkatasubramanian, Cheng-Hsin Hsu:
Enhancing situational awareness with adaptive firefighting drones: leveraging diverse media types and classifiers. MMSys 2022: 279-286 - 2021
- [c13]Bo-Jr Huang, Eric Jia-Wei Fang, Sung S.-Y. Hsueh, Rory Huang, Angus Lin, Chi-Hsun Chiang, Yi-Hsuan Lin, Wen-Wen Hsieh, Barry Chen, Yi-Chang Zhuang, Cheng-Yuh Wu, Jia-Ming Chen, Y. S. Chen, Cheng-Tien Wan, Ericbill Wang, Alex Chiou, Ping Kao, Yuwen Tsai, Harry H. Chen, Shih-Arn Hwang:
35.1 An Octa-Core 2.8/2GHz Dual-Gear Sensor-Assisted High-Speed and Power-Efficient CPU in 7nm FinFET 5G Smartphone SoC. ISSCC 2021: 490-492 - [c12]Yen-Ting Kuo, Wei-Chen Lin, Chun Chen, Chao-Ho Hsieh, James Chien-Mo Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh:
Minimum Operating Voltage Prediction in Production Test Using Accumulative Learning. ITC 2021: 47-52 - [c11]Min-Yan Su, Wei-Chen Lin, Yen-Ting Kuo, Chien-Mo James Li, Eric Jia-Wei Fang, Sung S.-Y. Hsueh:
Chip Performance Prediction Using Machine Learning Techniques. VLSI-DAT 2021: 1-4 - 2020
- [c10]Heng-Yi Lin, Yen-Chun Fang, Shi-Tang Liu, Jia-Xian Chen, Chien-Mo James Li, Eric Jia-Wei Fang:
Automatic IR-Drop ECO Using Machine Learning. ITC-Asia 2020: 7-12
2010 – 2019
- 2018
- [c9]Yen-Chun Fang, Heng-Yi Lin, Min-Yan Su, Chien-Mo James Li, Eric Jia-Wei Fang:
Machine-learning-based dynamic IR drop prediction for ECO. ICCAD 2018: 17 - [c8]Shih-Yao Lin, Yen-Chun Fang, Yu-Ching Li, Yu-Cheng Liu, Tsung-Shan Yang, Shang-Chien Lin, Chien-Mo James Li, Eric Jia-Wei Fang:
IR drop prediction of ECO-revised circuits using machine learning. VTS 2018: 1-6 - 2015
- [c7]Eric Jia-Wei Fang, Terry Chi-Jih Shih, Darton Shen-Yu Huang:
IR to routing challenge and solution for interposer-based design. ASP-DAC 2015: 226-230 - 2010
- [j4]Kuan-Hsien Ho, Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang:
ECO Timing Optimization Using Spare Cells and Technology Remapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 697-710 (2010) - [j3]Jia-Wei Fang, Yao-Wen Chang:
Area-I/O Flip-Chip Routing for Chip-Package Co-Design Considering Signal Skews. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 29(5): 711-721 (2010)
2000 – 2009
- 2009
- [j2]Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang:
An Integer-Linear-Programming-Based Routing Algorithm for Flip-Chip Designs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 28(1): 98-110 (2009) - [c6]Jia-Wei Fang, Martin D. F. Wong, Yao-Wen Chang:
Flip-chip routing with unified area-I/O pad assignments for package-board co-design. DAC 2009: 336-339 - 2008
- [c5]Jia-Wei Fang, Kuan-Hsien Ho, Yao-Wen Chang:
Routing for chip-package-board co-design considering differential pairs. ICCAD 2008: 512-517 - [c4]Jia-Wei Fang, Yao-Wen Chang:
Area-I/O flip-chip routing for chip-package co-design. ICCAD 2008: 518-522 - 2007
- [j1]Jia-Wei Fang, I-Jye Lin, Yao-Wen Chang, Jyh-Herng Wang:
A Network-Flow-Based RDL Routing Algorithmz for Flip-Chip Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(8): 1417-1429 (2007) - [c3]Jia-Wei Fang, Chin-Hsiung Hsu, Yao-Wen Chang:
An Integer Linear Programming Based Routing Algorithm for Flip-Chip Design. DAC 2007: 606-611 - [c2]Yen-Pin Chen, Jia-Wei Fang, Yao-Wen Chang:
ECO timing optimization using spare cells. ICCAD 2007: 530-535 - 2005
- [c1]Jia-Wei Fang, I-Jye Lin, Ping-Hung Yuh, Yao-Wen Chang, Jyh-Herng Wang:
A routing algorithm for flip-chip design. ICCAD 2005: 753-758
Coauthor Index
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