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Pilar Parra Fernández
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Journal Articles
- 2020
- [j3]Carlos Jesús Jiménez-Fernández
, Carmen Baena Oliva
, Pilar Parra Fernández
, Francisco Eugenio Potestad-Ordóñez
, Manuel Valencia-Barrero
:
An Academic Approach to FPGA Design Based on a Distance Meter Circuit. Rev. Iberoam. de Tecnol. del Aprendiz. 15(3): 123-128 (2020) - [j2]Francisco Eugenio Potestad-Ordóñez
, Manuel Valencia-Barrero
, Carmen Baena Oliva
, Pilar Parra Fernández
, Carlos Jesús Jiménez-Fernández
:
Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA. Sensors 20(23): 6909 (2020) - 2005
- [j1]Pilar Parra Fernández, Antonio J. Acosta, Raúl Jiménez, Manuel Valencia-Barrero
:
Selective Clock-Gating for Low-Power Synchronous Counters. J. Low Power Electron. 1(1): 11-19 (2005)
Conference and Workshop Papers
- 2018
- [c9]Francisco Eugenio Potestad-Ordóñez
, Carlos Jesús Jiménez-Fernández
, Carmen Baena Oliva
, Pilar Parra Fernández
, Manuel Valencia-Barrero
:
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher. DCIS 2018: 1-6 - 2010
- [c8]Javier Castro-Ramirez, Pilar Parra Fernández
, Antonio J. Acosta
:
Optimization of clock-gating structures for low-leakage high-performance applications. ISCAS 2010: 3220-3223 - 2009
- [c7]Javier Castro-Ramirez, Pilar Parra Fernández
, Antonio J. Acosta
:
Switching Noise Optimization in the Wake-Up Phase of Leakage-Aware Power Gating Structures. PATMOS 2009: 76-85 - 2007
- [c6]Javier Castro-Ramirez, Pilar Parra Fernández
, Manuel Valencia-Barrero
, Antonio J. Acosta
:
A switching noise vision of the optimization techniques for low-power synthesis. ECCTD 2007: 156-159 - [c5]Javier Castro-Ramirez, Pilar Parra Fernández
, Manuel Valencia-Barrero
, Antonio J. Acosta:
Asymmetric clock driver for improved power and noise performances. ISCAS 2007: 893-896 - 2006
- [c4]Raúl Jiménez, Pilar Parra Fernández
, Javier Castro-Ramirez, Manuel Sanchez-Raya
, Antonio J. Acosta:
Optimization of Master-Slave Flip-Flops for High-Performance Applications. PATMOS 2006: 439-449 - 2003
- [c3]Raúl Jiménez, Pilar Parra Fernández
, Pedro Sanmartín, Antonio J. Acosta:
A New Hybrid CBL-CMOS Cell for Optimum Noise/Power Application. PATMOS 2003: 491-500 - 2002
- [c2]Raúl Jiménez, Pilar Parra Fernández
, Pedro Sanmartín, Antonio J. Acosta:
A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches. PATMOS 2002: 209-218 - [c1]Pilar Parra Fernández
, Antonio J. Acosta, Manuel Valencia-Barrero:
Selective Clock-Gating for Low Power/Low Noise Synchronous Counters 1. PATMOS 2002: 448-457
Coauthor Index
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