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ORCIDBasavaraj Talawar
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- affiliation: National Institute of Technology Karnataka, Surathkal, India
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Journal Articles
- 2024
[j19]H. D. Kallinatha
, Sadhana Rai, Basavaraj Talawar:
A Detailed Study of SOT-MRAM as an Alternative to DRAM Primary Memory in Multi-Core Environment. IEEE Access 12: 7224-7243 (2024)- 2022
- [j18]Jayashree N., B. Sathish Babu, Basavaraj Talwar:
Decentralised priority-based shortest job first queue model for IoT gateways in fog computing. Int. J. Grid Util. Comput. 13(4): 414-424 (2022) - [j17]Anil Kumar, Basavaraj Talawar:
Knowledgeable network-on-chip accelerator for fast and accurate simulations using supervised learning algorithms and multiprocessing. Int. J. Intell. Eng. Informatics 10(2): 160-182 (2022) - [j16]Anil Kumar, Basavaraj Talawar:
LBF-NoC: Learning-Based Framework to Predict Performance, Power and Area for Network-On-Chip Architectures. J. Circuits Syst. Comput. 31(11): 2250196:1-2250196:26 (2022) - 2021
- [j15]Pramod Yelmewad, Basavaraj Talawar:
Parallel deterministic local search heuristic for minimum latency problem. Clust. Comput. 24(2): 969-995 (2021) - [j14]Pramod Yelmewad, Basavaraj Talawar:
Parallel Version of Local Search Heuristic Algorithm to Solve Capacitated Vehicle Routing Problem. Clust. Comput. 24(4): 3671-3692 (2021) - [j13]Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar:
FPGA friendly NoC simulation acceleration framework employing the hard blocks. Computing 103(8): 1791-1813 (2021) - 2020
- [j12]Bheemappa Halavar, Basavaraj Talawar:
Power and performance analysis of 3D network-on-chip architectures. Comput. Electr. Eng. 83: 106592 (2020) - [j11]Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar:
An Efficient FPGA-Based Network-on-Chip Simulation Framework Utilizing the Hard Blocks. Circuits Syst. Signal Process. 39(10): 5247-5271 (2020) - [j10]Anil Kumar, Basavaraj Talawar:
ELBA-NoC: ensemble learning-based accelerator for 2D and 3D network-on-chip architectures. Int. J. Comput. Sci. Eng. 23(4): 319-335 (2020) - [j9]Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar:
LBNoC: Design of Low-latency Router Architecture with Lookahead Bypass for Network-on-Chip Using FPGA. ACM Trans. Design Autom. Electr. Syst. 25(1): 9:1-9:26 (2020) - [j8]Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar:
P-NoC: Performance Evaluation and Design Space Exploration of NoCs for Chip Multiprocessor Architecture Using FPGA. Wirel. Pers. Commun. 114(4): 3295-3319 (2020) - 2019
- [j7]Pramod Yelmewad, Basavaraj Talawar:
Parallel iterative hill climbing algorithm to solve TSP on GPU. Concurr. Comput. Pract. Exp. 31(7) (2019) - [j6]Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar:
YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs. J. Circuits Syst. Comput. 28(12): 1950202:1-1950202:31 (2019) - [j5]Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar:
Analysis of cache behaviour and software optimizations for faster on-chip network simulations. Int. J. Syst. Assur. Eng. Manag. 10(4): 696-712 (2019) - [j4]Bheemappa Halavar, Ujjwal Pasupulety, Basavaraj Talawar:
Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures. Simul. Model. Pract. Theory 96 (2019) - 2017
- [j3]Adithya H. K. Upadhya, Basavaraj Talawar, Jeny Rajan:
GPU implementation of non-local maximum likelihood estimation method for denoising magnetic resonance images. J. Real Time Image Process. 13(1): 181-192 (2017) - 2013
- [j2]Basavaraj Talwar, Bharadwaj Amrutur:
Traffic engineered NoC for streaming applications. Microprocess. Microsystems 37(3): 333-344 (2013) - 2007
- [j1]Basavaraj Talwar, Pallapa Venkataram, Lalit M. Patnaik:
A Method for Resource and Service Discovery in MANETs. Wirel. Pers. Commun. 41(2): 301-323 (2007)
Conference and Workshop Papers
- 2020
- [c16]Mishal Shah, Mehnaz Yunus, Pavan Vachhani, Leslie Monis, Mohit P. Tahiliani, Basavaraj Talawar:
PowerDPDK: Software-Based Real-Time Power Measurement for DPDK Applications. NFV-SDN 2020: 13-18 - 2019
- [c15]Pramod Yelmewad, Aniket Kumar, Basavaraj Talawar:
MMAS on GPU for Large TSP Instances. ICCCNT 2019: 1-6 - [c14]Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar:
High-Performance NoCs Employing the DSP48E1 Blocks of the Xilinx FPGAs. ISQED 2019: 163-169 - [c13]Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar:
Design of an Adaptive and Reliable Network on Chip Router Architecture Using FPGA. VLSI-DAT 2019: 1-4 - [c12]Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar:
High-Performance NoC Simulation Acceleration Framework Employing the Xilinx DSP48E1 Blocks. VLSI-DAT 2019: 1-4 - 2018
- [c11]Anil Kumar, Basavaraj Talawar:
Machine Learning Based Framework to Predict Performance Evaluation of On-Chip Networks. IC3 2018: 1-6 - [c10]Ujjwal Pasupulety, Bheemappa Halavar, Basavaraj Talawar:
Accurate Power and Latency Analysis of a Through-Silicon Via(TSV). ICACCI 2018: 688-694 - [c9]Bheemappa Halavar, Basavaraj Talawar:
OP3DBFT: A Power and Performance Optimal 3D BFT NoC Architecture. ISDA (1) 2018: 923-933 - [c8]G. S. Sangeetha, Vignesh Radhakrishnan, Prabhu B. M. Prasad, Khyamling Parane, Basavaraj Talawar:
Trace-Driven Simulation and Design Space Exploration of Network-on-Chip Topologies on FPGA. ISED 2018: 129-134 - [c7]Ujjwal Pasupulety, Bheemappa Halavar, Basavaraj Talawar:
Thermal Aware Design for Through-Silicon Via (TSV) based 3D Network-on-Chip (NoC) Architectures. ISED 2018: 236-240 - [c6]Bheemappa Halavar, Basavaraj Talawar:
Floorplan Based Performance Evaluation of 3D Variants of Mesh and BFT Networks-on-Chip. SPCOM 2018: 282-286 - [c5]Khyamling Parane, Basavaraj Talawar, Prabhu B. M. Prasad:
YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAs. VLSID 2018: 67-72 - 2017
- [c4]Basavaraj Talawar, Pramod Yelmewad:
GPU-Based Iterative Hill Climbing Algorithm to Solve Symmetric Traveling Salesman Problem. TopHPC 2017: 221-241 - 2016
- [c3]Khyamling Parane, Prabhu B. M. Prasad, Basavaraj Talawar:
Cache analysis and software optimizations for faster on-chip network simulations. ICIIS 2016: 83-88 - 2015
- [c2]Basavaraj Talawar:
A Crossbar Interconnection Network in DNA. IPDPS Workshops 2015: 342-345 - 2009
- [c1]Basavaraj Talwar, Shailesh Kulkarni, Bharadwaj Amrutur:
Latency, Power and Performance Trade-Offs in Network-on-Chips by Link Microarchitecture Exploration. VLSI Design 2009: 163-168
Informal and Other Publications
- 2019
- [i1]Aditya K. Kamath, Leslie Monis, A. Tarun Karthik, Basavaraj Talawar:
Storage Class Memory: Principles, Problems, and Possibilities. CoRR abs/1909.12221 (2019)
Coauthor Index
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last updated on 2024-07-09 04:45 CEST by the dblp team
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