Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAs."

Khyamling Parane, Basavaraj Talawar, Prabhu B. M. Prasad (2018)

> Home

Details and statistics

DOI: 10.1109/VLSID.2018.39

access: closed

type: Conference or Workshop Paper

metadata version: 2024-02-05

- view
  authority control:
- export record
  dblp key:
  - conf/vlsid/ParaneTM18
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/conf/vlsid/ParaneTM18
Khyamling Parane, Basavaraj Talawar, Prabhu B. M. Prasad:
YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Using FPGAs. VLSID 2018: 67-72

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.