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ORCIDLeomar S. da Rosa Jr.
Leomar Soares da Rosa Jr. – Leomar S. da Rosa
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Journal Articles
- 2023
[j10]Tiago R. Balen
, Carlos J. González, Ingrid F. V. Oliveira, Leomar S. da Rosa Jr., Rafael Iankowski Soares, Rafael B. Schvittz, Nemitala Added, Eduardo L. A. Macchione, Vitor A. P. Aguiar, Marcilei Aparecida Guazzelli, Nilberto H. Medina, Paulo F. Butzen:
Evaluating the Reliability of Different Voting Schemes for Fault Tolerant Approximate Systems. J. Electron. Test. 39(4): 409-420 (2023)- 2022
- [j9]Julio Saraçol Domingues Júnior, Leomar Soares da Rosa Jr., Felipe de Souza Marques:
Migortho: A Design Automation Flow for QCA Circuits. IEEE Des. Test 39(2): 23-30 (2022) - 2021
- [j8]Stephano Machado Moreira Goncalves, Leomar S. da Rosa Jr., Felipe S. Marques:
SmartDR: Algorithms and Techniques for Fast Detailed Routing with Good Design Rule Handling. ACM Trans. Design Autom. Electr. Syst. 26(2): 9:1-9:38 (2021) - 2020
- [j7]Stéphano M. M. Gonçalves, Leomar S. da Rosa Jr., Felipe de Souza Marques:
DRAPS: A Design Rule Aware Path Search Algorithm for Detailed Routing. IEEE Trans. Circuits Syst. II Express Briefs 67-II(7): 1239-1243 (2020) - 2018
- [j6]Maicon Schneider Cardoso, Gustavo H. Smaniotto, Andrei A. O. Bubolz, Matheus T. Moreira, Leomar S. da Rosa Jr., Felipe de Souza Marques:
Libra: An Automatic Design Methodology for CMOS Complex Gates. IEEE Trans. Circuits Syst. II Express Briefs 65-II(10): 1345-1349 (2018) - 2017
- [j5]Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.:
Transistor Count Optimization in IG FinFET Network Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(9): 1483-1496 (2017) - 2016
- [j4]Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.:
Graph-Based Transistor Network Generation Method for Supergate Design. IEEE Trans. Very Large Scale Integr. Syst. 24(2): 692-705 (2016) - 2012
- [j3]Tiago Henrique Trojahn, Juliano Lucas Gonçalves, Júlio Carlos Balzano de Mattos, Luciano Volcan Agostini, Leomar Soares da Rosa Jr.:
Evaluating two implementations of the component responsible for decoding video and audio in the Brazilian digital TV middleware. Multim. Tools Appl. 57(2): 373-392 (2012) - 2011
- [j2]Tiago Henrique Trojahn, Juliano Lucas Gonçalves, Júlio Carlos Balzano de Mattos, Luciano Volcan Agostini, Leomar Soares da Rosa Jr.:
A comparative analysis of media processing component implementations for the Brazilian digital TV middleware. Int. J. Inf. Technol. Commun. Convergence 1(4): 391-409 (2011) - 2010
- [j1]Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, André Inácio Reis, Renato P. Ribas:
Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits. Microelectron. J. 41(4): 247-255 (2010)
Conference and Workshop Papers
- 2023
- [c43]Laura Quevedo Jurgina, Lui Gill Aquini, Rafael Iankowski Soares, Leomar Soares da Rosa Jr., Marilton Sanchotene de Aguiar, Tiago Thompsen Primo:
Alfaba: A Tangible Solution to Support Brazilian Dyslexic Students in their Literacy Process. EDUCON 2023: 1-9 - 2022
- [c42]Ingrid F. V. Oliveira, Matheus F. Pontes, Rafael B. Schvittz, Leomar S. da Rosa Jr., Paulo F. Butzen, Rafael Iankowski Soares:
Fault Tolerance Evaluation of Different Majority Voter Designs. ISCAS 2022: 185-189 - [c41]Matheus F. Pontes, Ingrid F. V. Oliveira, Rafael B. Schvittz, Leomar Soares da Rosa Jr., Paulo F. Butzen:
The Impact of Logic Gates Susceptibility in Overall Circuit Reliability Analysis. ISCAS 2022: 1610-1614 - [c40]Henrique Kessler, Marcelo Schiavon Porto, Leomar Soares da Rosa Jr., Vinicius V. Camargo:
Standard Cell and Supergates Designs: An Electrical Comparison on 4-Input Logic Functions. ISCAS 2022: 1744-1748 - [c39]Henrique Kessler, Murilo Bohlke, Leomar S. da Rosa, Marcelo Schiavon Porto, Vinicius V. Camargo:
Calibration of Logical Effort Transistor Sizing for On-the-Fly Low-Power Supergate Design. LASCAS 2022: 1-4 - [c38]Guilherme B. Manske, Clayton R. Farias, Paulo F. Butzen, Leomar S. da Rosa:
A Fast Approximate Function Generation Method to ATMR Architecture. LASCAS 2022: 1-4 - 2021
- [c37]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE 2021: 1026-1031 - 2020
- [c36]Henrique Kessler, Plinio Finkenauer, Thiago H. Both, Leomar Soares da Rosa Jr., Vinicius V. Camargo:
Evaluation of Non-Series-Parallel Structures for BTI-Aware Automated Design Methodologies. ISCAS 2020: 1-5 - [c35]Rafael B. Schvittz, Paulo F. Butzen, Leomar S. da Rosa:
Methods for Susceptibility Analysis of Logic Gates in the Presence of Single Event Transients. ITC 2020: 1-9 - [c34]Julio Saraçol Domingues Júnior, Leomar Soares da Rosa Jr., Felipe de Souza Marques:
A Straightforward Methodology for QCA Circuits Design. SBCCI 2020: 1-6 - 2019
- [c33]Stéphano M. M. Gonçalves, Leomar S. da Rosa, Felipe S. de Marques:
An Improved Heuristic Function for A∗-Based Path Search in Detailed Routing. ISCAS 2019: 1-5 - [c32]Vitor G. Lima, Guilherme Paim, Leandro M. G. Rocha, Leomar S. da Rosa Jr., Felipe S. Marques, Eduardo A. C. da Costa, Vinicius V. Camargo, Rafael Soares, Sergio Bampi:
Maximizing Side Channel Attack-Resistance and Energy-Efficiency of the STTL Combining Multi-Vt Transistors with Current and Capacitance Balancing. ISCAS 2019: 1-5 - [c31]Rafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa, Paulo F. Butzen:
An Improved Technique for Logic Gate Susceptibility Evaluation of Single Event Transient Faults. VLSI-SoC (Selected Papers) 2019: 69-88 - 2018
- [c30]Rafael B. Schvittz, Denis Teixeira Franco, Leomar S. da Rosa Jr., Paulo F. Butzen:
Probabilistic Method for Reliability Estimation of SP- Networks considering Single Event Transient Faults. ICECS 2018: 357-360 - [c29]Matheus F. Pontes, Paulo F. Butzen, Rafael B. Schvittz, Leomar S. da Rosa Jr., Denis Teixeira Franco:
The Suitability of the SPR-MP Method to Evaluate the Reliability of Logic Circuits. ICECS 2018: 433-436 - [c28]Rafael B. Schvittz, Matheus F. Pontes, Cristina Meinhardt, Denis Teixeira Franco, Lirida A. B. Naviner, Leomar S. da Rosa, Paulo F. Butzen:
Reliability evaluation of circuits designed in multi- and single-stage versions. LASCAS 2018: 1-4 - [c27]Stéphano M. M. Gonçalves, Leomar S. da Rosa, Felipe S. de Marques:
A New Technique Using Tunnel Shape Information to Improve Path Search in Detailed Routing. NEWCAS 2018: 243-247 - [c26]Maicon Schneider Cardoso, Gustavo H. Smaniotto, Andrei A. O. Bubolz, Leomar S. da Rosa Jr., Felipe S. Marques:
Area-Aware Design of Static CMOS Complex Gates. NEWCAS 2018: 282-286 - 2017
- [c25]Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.:
A post-processing methodology to improve the automatic design of CMOS gates at layout-level. ICECS 2017: 42-45 - [c24]Stephano Machado Moreira Goncalves, Leomar S. da Rosa Jr., Felipe de Souza Marques:
A survey of path search algorithms for VLSI detailed routing. ISCAS 2017: 1-4 - [c23]Gustavo H. Smaniotto, Regis Zanandrea, Maicon Schneider Cardoso, Renato Souza de Souza, Matheus T. Moreira, Felipe S. Marques, Leomar S. da Rosa Jr.:
Post-processing of supergate networks aiming cell layout optimization. ISCAS 2017: 1-4 - [c22]Maicon Schneider Cardoso, Gustavo H. Smaniotto, Joao Junior da Silva Machado, Matheus T. Moreira, Leomar S. da Rosa, Felipe de Souza Marques:
Transistor placement strategies for non-series-parallel cells. MWSCAS 2017: 523-526 - 2016
- [c21]Maicon Schneider Cardoso, Regis Zanandrea, Renato Souza de Souza, Joao Junior da Silva Machado, Leomar Soares da Rosa Jr., Felipe de Souza Marques:
Topological characteristics of logic networks generated by a graph-based methodology. LASCAS 2016: 343-346 - [c20]Gustavo H. Smaniotto, Joao Junior da Silva Machado, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa Jr.:
Optimizing cell area by applying an alternative transistor folding technique in an open source physical synthesis CAD tool. LASCAS 2016: 355-358 - [c19]Maicon Schneider Cardoso, Gustavo H. Smaniotto, Regis Zanandrea, Renato Souza de Souza, Leomar S. da Rosa, Felipe de Souza Marques:
Physical design of supergate cells aiming geometrical optimizations. MWSCAS 2016: 1-4 - [c18]Gustavo H. Smaniotto, Matheus T. Moreira, Adriel Mota Ziesemer, Felipe S. Marques, Leomar S. da Rosa:
Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding. MWSCAS 2016: 1-4 - 2015
- [c17]Maicon Schneider Cardoso, Leomar Soares da Rosa Jr., Felipe de Souza Marques:
Evaluating Geometric Aspects of Non-Series-Parallel Cells. SBCCI 2015: 16:1-16:6 - 2014
- [c16]Stephano Machado Moreira Goncalves, Leomar Soares da Rosa Jr., Felipe de Souza Marques:
A new general purpose line probe routing algorithm. ICECS 2014: 658-661 - [c15]Vinicius N. Possani, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar Soares da Rosa Jr.:
Exploring Independent Gates in FinFET-Based Transistor Network Generation. SBCCI 2014: 41:1-41:6 - 2013
- [c14]Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa Jr.:
Efficient transistor-level design of CMOS gates. ACM Great Lakes Symposium on VLSI 2013: 191-196 - [c13]Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
Transistor-level optimization of CMOS complex gates. LASCAS 2013: 1-4 - [c12]Vinicius N. Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe S. Marques, Leomar S. da Rosa Jr.:
Improving the methodology to build non-series-parallel transistor arrangements. SBCCI 2013: 1-6 - 2012
- [c11]Vinicius N. Possani, Felipe S. Marques, Leomar S. da Rosa Jr., Vinicius Callegaro, André Inácio Reis, Renato P. Ribas:
NSP kernel finder - A methodology to find and to build non-series-parallel transistor arrangements. SBCCI 2012: 1-6 - 2011
- [c10]Tiago Henrique Trojahn, Juliano Lucas Gonçalves, Júlio C. B. de Mattos, Luciano Volcan Agostini, Leomar Soares da Rosa Jr.:
Tests and Performance Analysis of Media Processing Implementations for the Middleware of Brazilian Digital TV System Using Different Scenarios. MUE 2011: 95-100 - 2010
- [c9]Mayler G. A. Martins, Leomar S. da Rosa Jr., Anders B. Rasmussen, Renato P. Ribas, André Inácio Reis:
Boolean factoring with multi-objective goals. ICCD 2010: 229-234 - [c8]Vinicius Callegaro, Felipe de Souza Marques, Carlos Eduardo Klock, Leomar Soares da Rosa Jr., Renato P. Ribas, André Inácio Reis:
SwitchCraft: a framework for transistor network design. SBCCI 2010: 49-53 - 2009
- [c7]Leomar S. da Rosa Jr., Felipe Ribeiro Schneider, Renato P. Ribas, André Inácio Reis:
Switch level optimization of digital CMOS gate networks. ISQED 2009: 324-329 - 2008
- [c6]Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas:
Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms. ACM Great Lakes Symposium on VLSI 2008: 407-410 - [c5]Tiago Muller Gil Cardoso, Leomar S. da Rosa Jr., Felipe de Souza Marques, Renato P. Ribas, André Inácio Reis:
Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering. ISQED 2008: 47-52 - 2007
- [c4]Felipe S. Marques, Leomar S. da Rosa Jr., Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
DAG based library-free technology mapping. ACM Great Lakes Symposium on VLSI 2007: 293-298 - [c3]Leomar S. da Rosa Jr., André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Felipe Ribeiro Schneider:
A comparative study of CMOS gates with minimum transistor stacks. SBCCI 2007: 93-98 - 2006
- [c2]Leomar S. da Rosa Jr., Felipe S. Marques, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
Fast disjoint transistor networks from BDDs. SBCCI 2006: 137-142 - 2003
- [c1]Leomar S. da Rosa Jr., Flávio Rech Wagner, Luigi Carro, Alexandre Carissimi, André Inácio Reis:
Scheduling Policy Costs on a JAVA Microcontroller. OTM Workshops 2003: 520-533
Informal and Other Publications
- 2020
- [i1]Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee:
Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR abs/2012.02530 (2020)
Coauthor Index
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