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ORCIDJan Moritz Joseph
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2020 – today
- 2024
[c41]José Cubero-Cascante, Arunkumar Vaidyanathan, Rebecca Pelke, Lorenzo Pfeifer, Rainer Leupers, Jan Moritz Joseph:
A Calibratable Model for Fast Energy Estimation of MVM Operations on RRAM Crossbars. AICAS 2024: 537-538- [c40]Felix Staudigl
, Jan Philipp Thoma, Christian Niesler, Karl J. X. Sturm, Rebecca Pelke, Dominik Germek, Jan Moritz Joseph, Tim Güneysu, Lucas Davi, Rainer Leupers:
NVM-Flip: Non-Volatile-Memory BitFlips on the System Level. SAT-CPS@CODASPY 2024: 11-20 - [c39]Rebecca Pelke, José Cubero-Cascante, Nils Bosbach, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph:
CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures. DATE 2024: 1-6 - [c38]Rebecca Pelke, Felix Staudigl, Niklas Thomas, Nils Bosbach, Mohammed Hossein, José Cubero-Cascante, Letícia Maria Veiras Bolzani, Rainer Leupers, Jan Moritz Joseph:
A Fully Automated Platform for Evaluating ReRAM Crossbars. LATS 2024: 1-6 - [c37]Lorenzo Pfeifer, M. Gross, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph:
Analysis of Thermal Side-Channel Attacks on Analog/Digital Computing-in-Memory Accelerators. LATS 2024: 1-4 - [i16]Rebecca Pelke, José Cubero-Cascante, Nils Bosbach, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph:
CLSA-CIM: A Cross-Layer Scheduling Approach for Computing-in-Memory Architectures. CoRR abs/2401.07671 (2024) - [i15]Rebecca Pelke, Felix Staudigl, Niklas Thomas, Nils Bosbach, Mohammed Hossein, José Cubero-Cascante, Leticia Bolzani Poehls, Rainer Leupers, Jan Moritz Joseph:
A Fully Automated Platform for Evaluating ReRAM Crossbars. CoRR abs/2403.13655 (2024) - 2023
- [c36]Felix Staudigl, Mohammed Hossein, Tobias Ziegler, Hazem Al Indari, Rebecca Pelke, Sebastian Siegel, Dirk J. Wouters, Dominik Sisejkovic, Jan Moritz Joseph, Rainer Leupers:
Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories. CODES+ISSS 2023: 44-45 - [c35]Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers:
Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware. DAC 2023: 1-6 - [c34]Ananda Samajdar, Jan Moritz Joseph, Tushar Krishna:
AIrchitect: Automating Hardware Architecture and Mapping Optimization. DATE 2023: 1-6 - [c33]Niko Zurstraßen, José Cubero-Cascante, Jan Moritz Joseph, Li Yichao, Xinghua Xie, Rainer Leupers:
par-gem5: Parallelizing gem5's Atomic Mode. DATE 2023: 1-6 - [c32]Niko Zurstraßen, Nils Bosbach, Jan Moritz Joseph, Lukas Jünger, Jan Henrik Weinstock, Rainer Leupers:
Efficient RISC-V-on-x64 Floating Point Simulation. ICCD 2023: 558-565 - [c31]Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Veiras Bolzani Poehls, Rainer Leupers:
Invited Paper: A Holistic Fault Injection Platform for Neuromorphic Hardware. LATS 2023: 1-6 - [c30]José Cubero-Cascante, Niko Zurstraßen, Jörn Nöller, Rainer Leupers, Jan Moritz Joseph:
parti-gem5: gem5's Timing Mode Parallelised. SAMOS 2023: 177-192 - [c29]Rebecca Pelke, Nils Bosbach, José Cubero-Cascante, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph:
Mapping of CNNs on multi-core RRAM-based CIM architectures. VLSI-SoC 2023: 1-6 - [i14]Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Leticia Bolzani Poehls, Rainer Leupers:
Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware. CoRR abs/2302.07655 (2023) - [i13]Felix Staudigl, Mohammed Hossein, Tobias Ziegler, Hazem Al Indari, Rebecca Pelke, Sebastian Siegel, Dirk J. Wouters, Dominik Sisejkovic, Jan Moritz Joseph, Rainer Leupers:
Work-in-Progress: A Universal Instrumentation Platform for Non-Volatile Memories. CoRR abs/2308.02400 (2023) - [i12]José Cubero-Cascante, Niko Zurstraßen, Jörn Nöller, Rainer Leupers, Jan Moritz Joseph:
parti-gem5: gem5's Timing Mode Parallelised. CoRR abs/2308.09445 (2023) - [i11]Rebecca Pelke, Nils Bosbach, José Cubero-Cascante, Felix Staudigl, Rainer Leupers, Jan Moritz Joseph:
Mapping of CNNs on multi-core RRAM-based CIM architectures. CoRR abs/2309.03805 (2023) - 2022
- [j5]Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Behnam Razi Perjikolaei, Alberto García-Ortiz, Thilo Pionteck:
Ratatoskr: An Open-Source Framework for In-Depth Power, Performance, and Area Analysis and Optimization in 3D NoCs. ACM Trans. Model. Comput. Simul. 32(1): 3:1-3:21 (2022) - [c28]Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers:
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation. AICAS 2022: 174-177 - [c27]Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers:
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. DATE 2022: 1181-1184 - [c26]Yee Yang Tan, Felix Staudigl, Lukas Jünger, Anna Drewes, Rainer Leupers, Jan Moritz Joseph:
EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs. FPL 2022: 334-341 - [c25]Nils Bosbach, Jan Moritz Joseph, Rainer Leupers, Lukas Jünger:
NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool. VLSI-SoC 2022: 1-6 - [i10]Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers:
X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation. CoRR abs/2204.01501 (2022) - [i9]Yee Yang Tan, Felix Staudigl, Lukas Jünger, Anna Drewes, Rainer Leupers, Jan Moritz Joseph:
EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs. CoRR abs/2206.11613 (2022) - [i8]Nils Bosbach, Lukas Jünger, Jan Moritz Joseph, Rainer Leupers:
NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool. CoRR abs/2207.11036 (2022) - 2021
- [c24]Jan Moritz Joseph, Lennart Bamberg, Geonhwa Jeong, Ruei-Ting Chien, Rainer Leupers, Alberto García-Ortiz, Tushar Krishna, Thilo Pionteck:
Bridging the Frequency Gap in Heterogeneous 3D SoCs through Technology-Specific NoC Router Architectures. ASP-DAC 2021: 197-203 - [c23]Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna:
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. ISQED 2021: 60-66 - [c22]Lennart Bamberg, Tushar Krishna, Jan Moritz Joseph:
Technology-aware Router Architectures for On-Chip-Networks in Heterogeneous Technologies. NANOCOM 2021: 17:1-17:7 - [c21]Jan Moritz Joseph, Murat Sezgin Baloglu, Yue Pan, Rainer Leupers, Lennart Bamberg:
NEWROMAP: mapping CNNs to NoC-interconnected self-contained data-flow accelerators for edge-AI. NOCS 2021: 15-20 - [i7]Ananda Samajdar, Jan Moritz Joseph, Matthew Denton, Tushar Krishna:
AIRCHITECT: Learning Custom Architecture Design and Mapping Space. CoRR abs/2108.08295 (2021) - [i6]Felix Staudigl, Hazem Al Indari, Daniel Schön, Dominik Sisejkovic, Farhad Merchant, Jan Moritz Joseph, Vikas Rana, Stephan Menzel, Rainer Leupers:
NeuroHammer: Inducing Bit-Flips in Memristive Crossbar Memories. CoRR abs/2112.01087 (2021) - 2020
- [c20]Anna Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Gunter Saake, Thilo Pionteck:
Optimising Operator Sets for Analytical Database Processing on FPGAs. ARC 2020: 30-44 - [c19]Ananda Samajdar, Jan Moritz Joseph, Yuhao Zhu, Paul N. Whatmough, Matthew Mattina, Tushar Krishna:
A Systematic Methodology for Characterizing Scalability of DNN Accelerators using SCALE-Sim. ISPASS 2020: 58-68 - [i5]Jan Moritz Joseph, Ananda Samajdar, Lingjun Zhu, Rainer Leupers, Sung Kyu Lim, Thilo Pionteck, Tushar Krishna:
Architecture, Dataflow and Physical Design Implications of 3D-ICs for DNN-Accelerators. CoRR abs/2012.12563 (2020)
2010 – 2019
- 2019
- [j4]Jan Moritz Joseph, Lennart Bamberg, Dominik Ermel, Behnam Razi Perjikolaei, Anna Drewes, Alberto García Ortiz, Thilo Pionteck:
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures. IEEE Access 7: 135145-135163 (2019) - [j3]Lennart Bamberg, Jan Moritz Joseph, Thilo Pionteck, Alberto García Ortiz:
Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment. Integr. 67: 60-72 (2019) - [j2]Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz:
Simulation environment for link energy estimation in networks-on-chip with virtual channels. Integr. 68: 147-156 (2019) - [c18]Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García Ortiz, Thilo Pionteck:
System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips. ICCD 2019: 409-412 - [c17]Daniele Passaretti, Jan Moritz Joseph, Thilo Pionteck:
Survey on FPGAs in Medical Radiology Applications: Challenges, Architectures and Programming Models. FPT 2019: 279-282 - [c16]Jan Moritz Joseph, Dominik Ermel, Tobias Drewes, Lennart Bamberg, Alberto García-Ortiz, Thilo Pionteck:
Area Optimization with Non-Linear Models in Core Mapping for System-on-Chips. MOCAST 2019: 1-4 - [i4]Jan Moritz Joseph, Lennart Bamberg, Dominik Ermel, Behnam Razi Perjikolaei, Anna Drewes, Alberto García-Ortiz, Thilo Pionteck:
NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures. CoRR abs/1909.04554 (2019) - [i3]Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García Ortiz, Thilo Pionteck:
System-level optimization of Network-on-Chips for heterogeneous 3D System-on-Chips. CoRR abs/1909.13807 (2019) - [i2]Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Behnam Razi Perjikolaei, Alberto García Ortiz, Thilo Pionteck:
Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs. CoRR abs/1912.05670 (2019) - 2018
- [c15]Tobias Drewes, Jan Moritz Joseph, Bala Gurumurthy, David Broneske, Gunter Saake, Thilo Pionteck:
Efficient Inter-Kernel Communication for OpenCL Database Operators on FPGAs. FPT 2018: 266-269 - [c14]Christopher Blochwitz, Julian Wolff, Mladen Berekovic, Dennis Heinrich, Sven Groppe, Jan Moritz Joseph, Thilo Pionteck:
Hardware-Accelerated Index Construction for Semantic Web. FPT 2018: 278-281 - [c13]Lennart Bamberg, Jan Moritz Joseph, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz:
Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels. PATMOS 2018: 222-228 - [c12]Jan Moritz Joseph, Lennart Bamberg, Gerald Krell, Imad Hajjar, Alberto García Ortiz, Thilo Pionteck:
Specification of Simulation Models for NoCs in Heterogeneous 3D SoCs. ReCoSoC 2018: 1-8 - 2017
- [j1]Jan Moritz Joseph, Christopher Blochwitz, Alberto García Ortiz, Thilo Pionteck:
Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs. Microprocess. Microsystems 48: 36-47 (2017) - [c11]Christopher Blochwitz, Julian Wolff, Jan Moritz Joseph, Stefan Werner, Dennis Heinrich, Sven Groppe, Thilo Pionteck:
Hardware-Accelerated Radix-Tree Based String Sorting for Big Data Applications. ARCS 2017: 47-58 - [c10]Christopher Blochwitz, Raphael Klink, Jan Moritz Joseph, Thilo Pionteck:
Continuous live-tracing as debugging approach on FPGAs. ReConFig 2017: 1-8 - [c9]Tobias Drewes, Jan Moritz Joseph, Thilo Pionteck:
An FPGA-based prototyping framework for Networks-on-Chip. ReConFig 2017: 1-7 - [c8]Jan Moritz Joseph, Morten Mey, Kristian Ehlers, Christopher Blochwitz, Tobias Winker, Thilo Pionteck:
Design space exploration for a hardware-accelerated embedded real-time pose estimation using vivado HLS. ReConFig 2017: 1-8 - [c7]Jan Moritz Joseph, Lennart Bamberg, Sven Wrieden, Dominik Ermel, Alberto García Ortiz, Thilo Pionteck:
Design method for asymmetric 3D interconnect architectures with high level models. ReCoSoC 2017: 1-8 - 2016
- [c6]Jan Moritz Joseph, Christopher Blochwitz, Thilo Pionteck:
Adaptive allocation of default router paths in Network-on-Chips for latency reduction. HPCS 2016: 140-147 - [c5]Jan Moritz Joseph, Tobias Winker, Kristian Ehlers, Christopher Blochwitz, Thilo Pionteck:
Hardware-accelerated pose estimation for embedded systems using Vivado HLS. ReConFig 2016: 1-7 - [c4]Jan Moritz Joseph, Sven Wrieden, Christopher Blochwitz, Alberto García Ortiz, Thilo Pionteck:
A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip. ReCoSoC 2016: 1-8 - 2015
- [c3]Jan Moritz Joseph, Christopher Blochwitz, Thilo Pionteck, Alberto García Ortiz:
Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs. NORCAS 2015: 1-4 - [c2]Christopher Blochwitz, Jan Moritz Joseph, Rico Backasch, Thilo Pionteck, Stefan Werner, Dennis Heinrich, Sven Groppe:
An optimized radix-tree for hardware-accelerated dictionary generation for semantic web databases. ReConFig 2015: 1-7 - 2014
- [c1]Jan Moritz Joseph, Thilo Pionteck:
A cycle-accurate Network-on-Chip simulator with support for abstract task graph modeling. ISSoC 2014: 1-6 - [i1]Jan Moritz Joseph, Jens Christian Claussen:
A model for dynamical evolution of science in space. CoRR abs/1407.8422 (2014)
Coauthor Index
aka: Letícia Maria Veiras Bolzani Poehls
aka: Letícia Maria Bolzani Pöhls
aka: Leticia Bolzani Poehls
aka: Alberto García-Ortiz
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last updated on 2024-10-01 21:43 CEST by the dblp team
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